TPS54140DGQR

@@ -53,7 +53,7 @@         "number": "1",         "name": "BOOT",         "type": "output",-        "description": "Bootstrap capacitor pin; requires 0.1\u03bcF ceramic capacitor to PH pin for gate-drive voltage; monitoring circuit forces high-side MOSFET off when boot voltage drops below 2.1V minimum threshold."+        "description": "Bootstrap capacitor pin; requires 0.1μF ceramic capacitor to PH pin for gate-drive voltage; monitoring circuit forces high-side MOSFET off when boot voltage drops below 2.1V minimum threshold."       },       {         "number": "2",@@ -65,13 +65,13 @@         "number": "3",         "name": "EN",         "type": "input",-        "description": "Enable pin with internal 0.9\u03bcA pullup current source; pull below 1.2V threshold to disable or float to enable; adjust input UVLO with external resistor divider."+        "description": "Enable pin with internal 0.9μA pullup current source; pull below 1.2V threshold to disable or float to enable; adjust input UVLO with external resistor divider."       },       {         "number": "4",         "name": "SS/TR",         "type": "input",-        "description": "Slow-start and tracking pin; external capacitor (0.47nF to 0.47\u03bcF) controls output voltage rise time; voltage overrides internal 0.8V reference for ratiometric sequencing applications."+        "description": "Slow-start and tracking pin; external capacitor (0.47nF to 0.47μF) controls output voltage rise time; voltage overrides internal 0.8V reference for ratiometric sequencing applications."       },       {         "number": "5",@@ -83,13 +83,13 @@         "number": "6",         "name": "PWRGD",         "type": "tri_state",-        "description": "Open-drain power good output; asserts low when VSENSE voltage is outside 92% to 107% window, during thermal shutdown exceeding 182\u00b0C, UVLO, or EN pin pulled below 1.25V."+        "description": "Open-drain power good output; asserts low when VSENSE voltage is outside 92% to 107% window, during thermal shutdown exceeding 182°C, UVLO, or EN pin pulled below 1.25V."       },       {         "number": "7",         "name": "VSENSE",         "type": "input",-        "description": "Inverting input node of transconductance error amplifier with 97\u03bcA/V gain; connect to resistor divider from output voltage for feedback comparison to internal 0.8V reference."+        "description": "Inverting input node of transconductance error amplifier with 97μA/V gain; connect to resistor divider from output voltage for feedback comparison to internal 0.8V reference."       },       {         "number": "8",@@ -150,6 +150,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "tps54140dgqr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.9,+          3.0,+          0.95+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "18605eed706df7bb9674107abe7aa36e0ba163a09c21a2cee6c75cfa291b7937",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "tps54140dgqr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.9,+          3.0,+          0.95+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "8c4af0201df04c1df66e1ff459f7a331c607493d81884286bd25b95cf169eed7",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}