TPS54062DRBT from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT	output	A bootstrap capacitor is required between BOOT and PH, and if its voltage falls below the minimum required by the output device the output is forced off until the capacitor is refreshed.
2	VIN	power_in	Input supply voltage, 4.7 V to 60 V.
3	EN	input	Enable pin with internal pull-up current source; pull below 1.14 V to disable and float to enable, and the input undervoltage lockout can be adjusted with two resistors.
4	RT/CLK	input	Resistor timing and external clock pin that holds a fixed voltage to set the switching frequency with a resistor to ground, or becomes a high-impedance PLL synchronization input when pulled above the PLL upper threshold.
5	VSENSE	input	Inverting input of the transconductance (gm) error amplifier.
6	COMP	output	Error amplifier output and input to the output switch current comparator, where frequency compensation components connect.
7	GND	power_in	Ground.
8	PH	output	Source of the internal high-side power MOSFET and drain of the internal low-side MOSFET.
9	Thermal Pad	power_in	The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation; this pad applies to the VSON-8 package only.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SON-8-EP(3x3)
Category	Power Management (PMIC)
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating input voltage	VIN	4.7		60	V		6
Input voltage		4.7		60	V		5
Output current				50	mA		5
Switching frequency set by RT/CLK resistor		100		400	kHz		5
Switching frequency synchronized to external clock		300		400	kHz		5
Input voltage absolute maximum	VIN	-0.3		62	V		5
EN voltage absolute maximum	EN	-0.3		8	V		5
BOOT-PH voltage absolute maximum	BOOT-PH	-0.3		8	V		5
VSENSE voltage absolute maximum	VSENSE	-0.3		6	V		5
COMP voltage absolute maximum	COMP	-0.3		3	V		5
PH voltage absolute maximum	PH	-0.6		62	V		5
PH voltage transient absolute maximum	PH	-2		62	V	10ns transient	5
RT/CLK voltage absolute maximum	RT/CLK	-0.3		6	V		5
EN current absolute maximum	EN			100	µA		5
BOOT current absolute maximum	BOOT			100	mA		5
VSENSE current absolute maximum	VSENSE			10	µA		5
COMP current absolute maximum	COMP			100	µA		5
RT/CLK current absolute maximum	RT/CLK			200	µA		5
Operating junction temperature	TJ	-40		125	°C		5
Storage temperature	Tsg	-65		150	°C		5
Junction-to-ambient thermal resistance (VSON)	RθJA		40.2		°C/W		6
Junction-to-case (top) thermal resistance (VSON)	RθJC(top)		49.7		°C/W		6
Junction-to-board thermal resistance (VSON)	RθJB		15.7		°C/W		6
Junction-to-case (bottom) thermal resistance (VSON)	RθJC(bot)		4.1		°C/W		6
Shutdown supply current			1.7		µA	EN = 0 V	6
Operating non-switching supply current	Iq		89	110	µA	VSENSE = 0.9 V, VIN = 12 V	6
Enable threshold rising		1.24		1.4	V	Rising	6
Enable threshold falling		1		1.14	V	Falling	6
Enable input current at threshold +50 mV			-4.7		µA	Enable threshold +50 mV	6
Enable input current at threshold -50 mV			-1.2		µA	Enable threshold -50 mV	6
Enable hysteresis current			3.5		µA	Hysteresis	6
Enable to start switching time			450		µs		6
VIN start voltage			4.53		V	VIN rising	6
Voltage reference	VREF	0.784	0.8	0.816	V	1mA < IOUT < Minimum Current Limit	6
High-side MOSFET switch resistance			1.5	2.8	Ω	BOOT-PH = 5.7 V	6
Low-side MOSFET switch resistance			0.8	1.5	Ω	VIN = 12 V	6
Error amplifier input current			20		nA	VSENSE pin	6
Error amplifier gm			102		µS	-2 µA < I(COMP) < 2 µA, V(COMP) = 1 V	6
EA gm during slow-start			26		µS	-2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, VSENSE = 0.4 V	6
Error amplifier DC gain			1000		V/V	VSENSE = 0.8 V	6
Error amplifier source/sink current		-8		8	µA	V(COMP) = 1 V, 100-mV Overdrive	6
Start switching threshold			0.57		V		6
COMP to Iswitch gm			0.65		A/V		6
High-side sourcing current limit threshold		75	134		mA	VIN = 12V, BOOT-PH = 5.7 V	6
Thermal shutdown			146		C		7
Operating frequency using RT mode		100		400	kHz		7
Switching frequency		192	240	288	kHz	R(RT/CLK) = 510 kΩ	7
Minimum CLK pulse width			40		ns		7
RT/CLK voltage			0.53		V	R(RT/CLK) = 510 kΩ	7
RT/CLK high threshold			1.3		V		7
RT/CLK low threshold			0.5		V		7
RT/CLK falling edge to PH rising edge delay		100		200	ns	Measure at 240 kHz with RT resistor in series	7
PLL lock in time			100		µs	Measure at 240 kHz	7
PLL frequency range		300		400	kHz		7
Minimum on-time			120		ns	Measured at 50% to 50% of VIN, IOUT = 50 mA	7
Dead time			30		ns	VIN = 12V, IOUT = 50 mA, One transition	7
BOOT-PH regulation voltage			5.7		V	VIN = 12 V	7
BOOT-PH UVLO			2.9		V		7
Slow-start time			4.1		ms	fSW = 240 kHz, RT = 510 kΩ, 10% to 90%	7

CAD (KiCad official)

Symbol: TPS54062DRBT
Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
3D model files: tps54062drbt-etched.step / tps54062drbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54062drbt.step / tps54062drbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (44 pp, sha256 6c49a9788f84977e, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS54062DRBT

Verified TPS54062DRBT

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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