component
TPS54061QDRBTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54061QDRBTQ1
Texas Instruments · DC-DC Converters · SON-8-EP(3x3)
TPS54061QDRBTQ1 from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Requires a bootstrap capacitor between BOOT and PH; if the capacitor voltage falls below the minimum required by the output device, the output switches off until the capacitor is refreshed. |
| 2 | VIN | power_in | Input supply voltage, 4.7 V to 60 V. |
| 3 | EN | input | Enable pin with internal pullup current source; pull below 1.18 V to disable, float to enable, and use two resistors to adjust the input undervoltage lockout. |
| 4 | RT/CLK | input | Resistor to ground sets the switching frequency; pulling the pin above the PLL upper threshold turns it into a high-impedance synchronization clock input to the internal PLL. |
| 5 | VSENSE | input | Inverting input of the transconductance (gm) error amplifier. |
| 6 | COMP | passive | Error amplifier output and input to the output switch current comparator; connect frequency compensation components to this pin. |
| 7 | GND | power_in | Ground. |
| 8 | PH | output | Source of the internal high-side power MOSFET and drain of the internal low-side MOSFET (switching node). |
| 9 | PowerPAD | power_in | Thermal pad; connect electrically to the GND pin on the printed circuit board for proper operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SON-8-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VIN pin) | VIN | -0.3 | 62 | V | 4 | ||
| EN pin voltage | EN | -0.3 | 8 | V | 4 | ||
| BOOT-PH voltage | BOOT-PH | 8 | V | 4 | |||
| BOOT voltage | BOOT | 70 | V | 4 | |||
| VSENSE voltage | VSENSE | -0.3 | 6 | V | 4 | ||
| COMP voltage | COMP | -0.3 | 3 | V | 4 | ||
| PH voltage | PH | -0.6 | 62 | V | 4 | ||
| PH voltage transient | PH | -2 | 62 | V | 10-ns transient | 4 | |
| RT/CLK voltage | RT/CLK | -0.3 | 6 | V | 4 | ||
| BOOT current | 100 | mA | 4 | ||||
| Operating junction temperature | -40 | 150 | °C | 4 | |||
| Storage temperature | -65 | 150 | °C | 4 | |||
| Electrostatic discharge, Human Body Model (HBM) | 2 | kV | JESD22-A114A, AEC-Q100 Classification Level H2 | 4 | |||
| Electrostatic discharge, Charged Device Model (CDM) | 750 | V | JESD22-C101B.01, AEC-Q100 Classification Level C3B | 4 | |||
| Operating input voltage | VIN | 4.7 | 60 | V | 5 | ||
| Enable threshold, rising | 1.23 | 1.4 | V | 5 | |||
| Enable threshold, falling | 1 | 1.18 | V | 5 | |||
| Voltage reference | VREF | 0.792 | 0.8 | 0.808 | V | TJ = 25°C, VIN = 12 V | 5 |
| Voltage reference | VREF | 0.784 | 0.8 | 0.816 | V | 1 mA < IOUT < Minimum current limit | 5 |
| High-side MOSFET switch resistance | 1.5 | 3 | Ω | BOOT-PH = 5.7 V | 5 | ||
| Low-side MOSFET switch resistance | 0.8 | 1.5 | Ω | VIN = 12 V | 5 | ||
| Error amplifier source and sink current | -8 | 8 | µA | V(COMP) = 1 V, 100 mV overdrive | 5 | ||
| High-side sourcing current-limit threshold | 250 | 350 | 500 | mA | BOOT-PH = 5.7 V | 5 | |
| Operating frequency using RT mode | 50 | 1100 | kHz | 5 | |||
| PLL frequency range | 300 | 1100 | kHz | 6 | |||
| Supply current, shutdown | 1.4 | µA | EN = 0 V | 5 | |||
| Iq operating, non-switching | Iq | 90 | 110 | µA | VSENSE = 0.9 V, VIN = 12 V | 5 | |
| Enable pin input current | -4.7 | µA | Enable threshold 50 mV | 5 | |||
| Enable pin input current | -1.2 | µA | Enable threshold -50 mV | 5 | |||
| Enable hysteresis current | -3.5 | µA | 5 | ||||
| Enable high to start switching time | 450 | µs | 5 | ||||
| VIN start voltage | 4.5 | V | VIN rising | 5 | |||
| Error amplifier input current | 20 | nA | VSENSE pin | 5 | |||
| Error-amplifier gm | 108 | µMhos | -2 µA < I(COMP) < 2 µA, V(COMP) = 1 V | 5 | |||
| EA gm during slow start | 27 | µMhos | -2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, VSENSE = 0.4 V | 5 | |||
| Error amplifier dc gain | 1000 | V/V | VSENSE = 0.8 V | 5 | |||
| Minimum unity-gain bandwidth | 0.5 | MHz | 5 | ||||
| Start-switching threshold | 0.57 | V | 5 | ||||
| COMP to Iswitch gm | 1 | A/V | 5 | ||||
| Zero-cross detect current | -1.1 | mA | 5 | ||||
| Thermal shutdown | 176 | °C | 5 | ||||
| Switching frequency | 425 | 472 | 520 | kHz | R(RT/CLK) = 120 kΩ | 5 | |
| Minimum CLK pulse duration | 40 | ns | 5 | ||||
| RT/CLK voltage | 0.53 | V | R(RT/CLK) = 120 kΩ | 5 | |||
| RT/CLK high threshold | 1.8 | V | 5 | ||||
| RT/CLK low threshold | 0.5 | V | 5 | ||||
| RT/CLK falling-edge to PH rising-edge delay | 67 | ns | Measure at 500 kHz with RT resistor | 5 | |||
| PLL lock-in time | 100 | µs | Measure at 500 kHz | 5 | |||
| Minimum on-time | 120 | ns | Measured at 50% to 50%, IOUT = 200 mA | 6 | |||
| Dead time | 30 | ns | VIN = 12 V, IOUT = 200 mA, one transition | 6 | |||
| BOOT-to-PH regulation voltage | 6 | V | VIN = 12 V | 6 | |||
| BOOT-PH UVLO | 2.9 | V | 6 | ||||
| Slow-start time | 2.36 | ms | fSW = 472 kHz, RT = 120 kΩ, 10% to 90% | 6 | |||
| Junction-to-ambient thermal resistance | θJA | 42.9 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | θJCtop | 46 | °C/W | 4 | |||
| Junction-to-board thermal resistance | θJB | 18.1 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 0.5 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ψJB | 18.3 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance | θJCbot | 3 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TPS54061QDRBTQ1 - Footprint:
Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm - 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps54061qdrbtq1-etched.step/tps54061qdrbtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54061qdrbtq1.step/tps54061qdrbtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
013211c331e55e03, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).