# TPS54061DRBR

**Texas Instruments** · DC-DC Converters · SON-8-EP(3x3)

TPS54061DRBR from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | A bootstrap capacitor is required between BOOT and PH, and if the voltage on this capacitor falls below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. |
| 2 | VIN | power_in | Input supply voltage, 4.7 V to 60 V. |
| 3 | EN | input | Enable pin with internal pull-up current source; pull below 1.18 V to disable and float to enable, and the input undervoltage lockout (UVLO) can be adjusted with two resistors. |
| 4 | RT/CLK | input | Resistor timing and external clock pin; an internal amplifier holds this pin at a fixed voltage when an external resistor to ground sets the switching frequency, and it becomes a synchronization input when pulled above the PLL upper threshold. |
| 5 | VSENSE | input | Inverting input of the transconductance (gm) error amplifier. |
| 6 | COMP | output | Error amplifier output and input to the output switch current comparator, where frequency compensation components connect. |
| 7 | GND | power_in | Ground. |
| 8 | PH | output | The source of the internal high-side power MOSFET and drain of the internal low-side MOSFET. |
| 9 | Thermal Pad | power_in | Thermal GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SON-8-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating input voltage | VIN | 4.7 |  | 60 | V |  | 5 |
| Enable threshold falling | EN | 1 | 1.18 |  | V |  | 5 |
| Enable threshold rising | EN |  | 1.23 | 1.4 | V |  | 5 |
| Voltage reference | VREF | 0.792 | 0.8 | 0.808 | V | TJ = 25°C, VIN = 12 V | 5 |
| Voltage reference | VREF | 0.784 | 0.8 | 0.816 | V | 1mA < IOUT < Minimum Current Limit | 5 |
| Operating non-switching supply current | IQ |  | 90 | 110 | µA | VSENSE = 0.9 V, VIN = 12 V | 5 |
| High-side MOSFET switch resistance | RDS(on) |  | 1.5 | 3 | Ω | BOOT-PH = 5.7 V | 5 |
| Low-side MOSFET switch resistance | RDS(on) |  | 0.8 | 1.5 | Ω | VIN = 12 V | 5 |
| Error amplifier source/sink current |  | -8 |  | 8 | µA | V(COMP) = 1 V, 100 mV Overdrive | 5 |
| High-side sourcing current limit threshold |  | 250 | 350 | 500 | mA | BOOT-PH = 5.7 V | 5 |
| Operating frequency using RT mode | fSW | 50 |  | 1100 | kHz |  | 5 |
| Switching frequency | fSW | 425 | 472 | 520 | kHz | R(RT/CLK) = 120 kΩ | 5 |
| PLL frequency range |  | 300 |  | 1100 | kHz |  | 5 |
| VIN input voltage recommended operating range | VIN | 4.7 |  | 60 | V |  | 4 |
| Output current | IOUT |  |  | 200 | mA |  | 4 |
| Switching frequency set by RT/CLK resistor | fSW | 50 |  | 1100 | kHz |  | 4 |
| Switching frequency synchronized to external clock | fSW | 300 |  | 1100 | kHz |  | 4 |
| VIN absolute maximum voltage | VIN | -0.3 |  | 62 | V |  | 4 |
| EN absolute maximum voltage | EN | -0.3 |  | 8 | V |  | 4 |
| BOOT-PH absolute maximum voltage | BOOT-PH | -0.3 |  | 8 | V |  | 4 |
| VSENSE absolute maximum voltage | VSENSE | -0.3 |  | 6 | V |  | 4 |
| COMP absolute maximum voltage | COMP | -0.3 |  | 3 | V |  | 4 |
| PH absolute maximum voltage | PH | -0.6 |  | 62 | V |  | 4 |
| PH 10 ns transient voltage | PH | -4 |  | 62 | V | 10 ns transient | 4 |
| RT/CLK absolute maximum voltage | RT/CLK | -0.3 |  | 6 | V |  | 4 |
| BOOT absolute maximum current | BOOT |  |  | 100 | mA |  | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 42.9 |  | °C/W |  | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 46 |  | °C/W |  | 4 |
| Junction-to-board thermal resistance | RθJB |  | 18.1 |  | °C/W |  | 4 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 3 |  | °C/W |  | 4 |
| Junction-to-top characterization parameter | ψJT |  | 0.5 |  | °C/W |  | 4 |
| Junction-to-board characterization parameter | ψJB |  | 18.3 |  | °C/W |  | 4 |
| Shutdown supply current |  |  | 1.4 |  | µA | EN = 0 V | 5 |
| Enable threshold hysteresis input current, +50 mV |  |  | -4.7 |  | µA | Enable threshold +50 mV | 5 |
| Enable threshold hysteresis input current, -50 mV |  |  | -1.2 |  | µA | Enable threshold -50 mV | 5 |
| Enable hysteresis current | Ihys |  | -3.5 |  | µA |  | 5 |
| Enable high to start switching time |  |  | 450 |  | µs |  | 5 |
| VIN start voltage | VIN |  | 4.5 |  | V | VIN rising | 5 |
| Error amp input current |  |  | 20 |  | nA | VSENSE pin | 5 |
| Error amp gm | gm |  | 108 |  | µS | -2µA < I(COMP) < 2µA, V(COMP) = 1 V | 5 |
| Error amp gm during slow start | gm |  | 27 |  | µS | -2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, VSENSE = 0.4 V | 5 |
| Error amp DC gain |  |  | 1000 |  | V/V | VSENSE = 0.8V | 5 |
| Minimum unity gain bandwidth |  |  | 0.5 |  | MHz |  | 5 |
| Start-switching threshold |  |  | 0.57 |  | V |  | 5 |
| COMP to Iswitch gm | gm |  | 1 |  | A/V |  | 5 |
| Zero cross detect current |  |  | -1.1 |  | mA |  | 5 |
| Thermal shutdown |  |  | 176 |  | C |  | 5 |
| Minimum CLK pulsewidth |  |  | 40 |  | ns |  | 5 |
| RT/CLK voltage |  |  | 0.53 |  | V | R(RT/CLK) = 120 kΩ | 5 |
| RT/CLK high threshold |  |  | 1.8 |  | V |  | 5 |
| RT/CLK low threshold |  |  | 0.5 |  | V |  | 5 |
| RT/CLK falling edge to PH rising edge delay |  |  | 60 |  | ns | Measure at 500 kHz with RT resistor | 5 |
| PLL lock in time |  |  | 100 |  | µs | Measure at 500 kHz | 5 |
| Minimum on-time |  |  | 120 |  | ns | Measured at 50% to 50%, IOUT = 200 mA | 6 |
| Dead time |  |  | 30 |  | ns | VIN = 12 V, IOUT = 200 mA, One transition | 6 |
| BOOT to PH regulation voltage |  |  | 6 |  | V | VIN = 12 V | 6 |
| BOOT-PH UVLO |  |  | 2.9 |  | V |  | 6 |
| Internal slow-start time |  |  | 2.36 |  | ms | fSW = 472 kHz, RT = 120 kΩ, 10% to 90% | 6 |

## CAD (KiCad official)

- Symbol: `TPS54061DRBR`
- Footprint: `Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm`
- 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `tps54061drbr-etched.step` / `tps54061drbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54061drbr.step` / `tps54061drbr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps54061.pdf) (40 pp, sha256 `4893c253fc9cc12c`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54061drbr-datasheet.pdf)