component

TPS53681RSBR

Public Made by Adom

by adom

Texas Instruments DC-DC Controllers, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icstps53681rsbrfactory-2.0.0extractor-text

Verified TPS53681RSBR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS53681RSBR · QFN-40-EP(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 131-page datasheet
  • ✓distributor: lcsc C702271, digikey TPS53681RSBR-ND, mouser 595-TPS53681RSBR
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5exo29bc/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.128)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps53681rsbr.kicad_sym✓ tps53681rsbr.kicad_mod✓ tps53681rsbr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers tps53681rsbr: viewers · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago
tps53681rsbr-etched.glb Publish 0.1.0 · Ray 7d ago
tps53681rsbr-etched.step tps53681rsbr: factory component page (tier=mfr) · Ray 7d ago
tps53681rsbr-hero.glb tps53681rsbr: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
tps53681rsbr-hero.overlay.json Publish 0.1.0 · Ray 7d ago
tps53681rsbr.glb Publish 0.1.0 · Ray 7d ago
tps53681rsbr.kicad_mod Publish 0.1.0 · Ray 7d ago
tps53681rsbr.kicad_sym Publish 0.1.0 · Ray 7d ago
tps53681rsbr.lbr Publish 0.1.0 · Ray 7d ago
tps53681rsbr.step Publish 0.1.0 · Ray 7d ago
verification.json Verified: Published by the parts factory: tier mfr, 41 pins · Ray 7d ago

TPS53681RSBR

Texas Instruments · DC-DC Controllers · QFN-40-EP(5x5)

TPS53681RSBR from Texas Instruments, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BPWM1 output PWM signal for phase 1 of channel B.
2 BPWM2 output PWM signal for phase 2 of channel B.
3 APWM6/BPWM3 output PWM signal for phase 6 of channel A, or phase 3 of channel B, based on the NVM option.
4 APWM5 output PWM signal for phase 5 of channel A.
5 APWM4 output PWM signal for phase 4 of channel A.
6 APWM3 output PWM signal for phase 3 of channel A.
7 APWM2 output PWM signal for phase 2 of channel A.
8 APWM1 output PWM signal for phase 1 of channel A.
9 SMB_DIO bidirectional SMBus or I2C bi-directional serial data interface (open drain).
10 SMB_CLK input SMBus or I2C serial clock interface (open drain).
11 SMB_ALERT bidirectional SMBus or I2C bi-directional ALERT pin interface (open drain).
12 AVR_RDY output Channel A power-good open-drain output requiring an external pull-up resistor; pulled low when a shutdown fault occurs.
13 AVR_EN input Active-high enable input for channel A; re-cycling BVR_EN pin clears the faults of channel A per the datasheet.
14 VR_HOT output Active-low external temperature indicator.
15 RESET bidirectional Resets the output voltage to the BOOT voltage.
16 BVR_RDY output Channel B power-good open-drain output requiring an external pull-up resistor; pulled low when a shutdown fault occurs.
17 GND power_in Connect to GND.
18 GND power_in Connect to GND.
19 NC unconnected No connection.
20 BVR_EN input Active-high enable input for channel B; re-cycling the pin clears the faults of channel B.
21 AVSP input Positive input of the remote voltage sense of channel A.
22 AVSN input Negative input of the remote voltage sense of channel A.
23 ACSP1 input Current sense input for channel A; connect to the IOUT pin of TI smart power stages.
24 ACSP2 input Current sense input for channel A; tie to V3P3 according to Table 1 to disable the phase.
25 ACSP3 input Current sense input for channel A; tie to V3P3 according to Table 1 to disable the phase.
26 ACSP4 input Current sense input for channel A; tie to V3P3 according to Table 1 to disable the phase.
27 ACSP5 input Current sense input for channel A; tie to V3P3 according to Table 1 to disable the phase.
28 ACSP6/BCSP3 input Current sense input for channel A or channel B based on NVM option; connect to IOUT of smart power stages, tie to the 3.3-V supply to disable the phase.
29 BCSP2 input Current sense input for channel B; connect to IOUT of smart power stages, tie to V3P3 according to Table 1 to disable the phase.
30 BVSP input Positive input of the remote voltage sense of channel B; connect to GND if channel B is not used.
31 BVSN input Negative input of the remote voltage sense of channel B; connect to GND if channel B is not used.
32 BCSP1 input Current sense input for channel B; connect to IOUT pins of TI smart power stages, or to GND if channel B is not used.
33 VR_FAULT output Open-drain VR fault indicator for high-side FET short, over-voltage, over-temperature and input over-current; low on failure and puts the controller into latch-off mode.
34 ADDR input Voltage divider to VREF and GND whose level sets the 7-bit PMBus address with an ADC, latched at 3.3-V power up.
35 BTSEN output Connect to TAO pin of TI smart power stages of channel B to sense the highest power-stage temperature and built-in fault signal.
36 ATSEN output Connect to TAO pin of TI smart power stages of channel A to sense the highest power-stage temperature and built-in fault signal.
37 CSPIN input Input voltage from the positive terminal of the input current sensing shunt; short to VIN_CSNIN and connect to converter input voltage (example: 12 V) when not used.
38 VIN_CSNIN power_in Input voltage sensing for on-time control and telemetry and negative terminal of the input current sense shunt; short to CSPIN and connect to converter input (example: 12 V) when not used.
39 V3P3 power_in 3.3-V power input for all digital logic circuits; bypass to GND with a ceramic capacitor of at least 1 µF.
40 VREF power_out 1.7-V LDO reference voltage; bypass to GND with 1-µF ceramic capacitor and connect to REFIN of TI smart power stages as current sense common-mode voltage.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-40-EP(5x5)
Category Power Management ICs
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage CSPIN, VIN_CSNIN -0.3 19 V 6
Input voltage ACSPx, ADDR, TSEN, EN, VSP, V3P3, RESET, SMB -0.3 3.6 V 6
Input voltage AGND, AVSN, BVSN -0.3 0.3 V 6
Output voltage PWM, RDY, ALERT, VREF, FAULT, HOT -0.3 3.6 V 6
Operating junction temperature TJ -40 150 °C 6
Storage temperature TSTG -55 150 °C 6
ESD HBM V(ESD) -3000 3000 V ANSI/ESDA/JEDEC JS-001 6
ESD CDM V(ESD) -1500 1500 V JESD22-C101 6
Input voltage CSPIN, VIN_CSNIN 4.5 12 17 V 6
Input voltage V3P3 2.97 3.3 3.5 V 6
Input voltage ACSPx, ADDR, TSEN, EN, VSP, RESET, SMB -0.1 3.5 V 6
Input voltage AGND, AVSN, BVSN -0.1 0.1 V 6
Output voltage VREF -0.1 1.72 V 6
Output voltage PWM, RDY, ALERT, FAULT, HOT -0.1 3.5 V 6
Ambient temperature TA -40 125 °C 6
Junction-to-ambient thermal resistance RθJA 34.1 °C/W RSB (WQFN) 40 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 16.6 °C/W 7
Junction-to-board thermal resistance RθJB 5.8 °C/W 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 0.9 °C/W 7
V3P3 supply current IV3P3 13 18 mA VDAC < VSP < VDAC + 100m V, ENABLE = 'HI' 7
V3P3 standby current IV3P3SBY 9 13.5 mA ENABLE = 'LO' 7
V3P3 normal range V3NORMAL 2.97 3.5 V Normal operation 7
V3P3 UVLO 'OK' threshold V3UVLOH 2.85 2.95 V Ramp up 7
V3P3 UVLO fault threshold V3UVLOL 2.65 2.75 V Ramp down 7
VSP tolerance VDAC0 -10 10 mV 10 mV DAC : 0.50 ≤ VVSP ≤ 0.99 V, ICORE = 0 A 8
VSP tolerance VDAC1 -8 8 mV 5 mV DAC: 0.25 ≤ VVSP ≤ 0.795 V, ICORE = 0 A 8
VSP tolerance VDAC2 -5 5 mV 5 mV DAC: 0.8 ≤ VVSP ≤ 0.995 V, ICORE = 0 A 8
VSP tolerance VDAC3 -0.5 0.5 % 5mV DAC: 1.00V ≤ VSP ≤ 1.52 V, ICORE = 0 A 8
VREF output deeper sleep VVREF 1.692 1.7 1.708 V 2.97V ≤ VV3P3 ≤ 3.5 V, IVREF = 0 A 8
AVSP input bias current IAVSP 75 µA Not in Fault, Disable or UVLO; VVSP = VVDAC = 2.3 V, VVSN = 0 V 8
AVSN input bias current IAVSN -75 µA Not in Fault, Disable or UVLO; VVSP = VVDAC = 2.3 V, VVSN = 0 V 8
MFR_READ_VOUT accuracy VREAD_VOUT -12 12 mV 5 mV DAC : 0.25 V ≤ VVSP ≤ 1.52 V; 10 mV DAC: 0.5 ≤ VVSP ≤ 2.4 V 9
READ_VIN accuracy VREAD_VIN -2.25 2.25 % 4.50 V ≤ VIN ≤ 17 V 9
READ_TEMP1 accuracy Temp -2 0 2 °C 0.28 V (-40°C) ≤ TSEN ≤ 1.8 V (150°C) 9
READ_IIN accuracy IIN -3 3 % (VCSPIN, VCSNIN) = 15 mV, IIN = 30 A, RSENSE = 0.5 mΩ 10
ACSP1 leakage current IACSP1 0 20 µA VACSP1 = 2.5 V 15
Open-drain pulldown resistance RRPGDL 36 50 Ω VAVR_RDY = VBVR_RDY = VVR_FAULT = 0.45 V 15
Open-drain leakage current IVRTTLK -2 0.2 2 µA SDIO, VR_HOT, AVR_RDY, BVR_RDY, VR_FAULT, Hi Z Leakage, apply to 3.3-V supply in off state 15
Channel A ENABLE logic low VAENL 0.7 V 15
Channel A ENABLE logic high VAENH 0.8 V 15
Channel A ENABLE hysteresis VAENHYS 0.028 0.05 0.07 V 15
RESET logic low VRSTL 0.8 V 15
Channel A startup time tSTARTUPA 0.38 0.48 0.58 ms VVBOOT > 0 V, no faults, CREF = 1 µF, TON_DELAY = 0xB1EC (PAGE 0) 16
VR_HOT update time tVRTDGLT 0.3 0.5 ms Temperature data update time 16
Switching frequency fSW 450 500 550 kHz FREQUENCY_SWITCH = 0x01F4; VIN = 12 V, VAVSP = 1.0 V, VBVSP = 0.8 V, TA = 25°C 19
Fixed overvoltage protection, Channel A VOVPA 2.75 2.8 2.86 V VAVSP > VOVP for 1 µs, ENABLE = HI or LO, PWM to LO 22
Fixed overvoltage protection, Channel B VOVPB 1.85 1.9 1.95 V VBVSP > VOVP for 1 µs, ENABLE = HI or LO, PWM to LO 22
Undervoltage protection VRDYL 370 400 430 mV (VVSP + VDROOP) with respect to VID 22
TSEN leakage current ITSEN -3 3 µA 22
PWMx output low-level VPWML 0.15 0.3 V ILOAD = 0.5 mA 23
PWMx output high-level VPWMH 2.8 V ILOAD = -0.5 mA; VV3P3 = 2.97 V 23
PWMx tri-state VPW-SKLK 1.6 1.7 1.8 V ILOAD = ± 100 µA 23

CAD (KiCad official)

  • Symbol: TPS53681RSBR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps53681rsbr-etched.step / tps53681rsbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53681rsbr.step / tps53681rsbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (131 pp, sha256 1e01d86e076acf18, retrieved 2026-10-31, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF