component

TPS53667RTAT

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps53667rtatfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers tps53667rtat: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/tps53667rtat · Ray 1d ago
tps53667rtat-etched.glb tps53667rtat: factory component page (tier=lcsc) · Ray 1d ago
tps53667rtat-etched.step tps53667rtat: factory component page (tier=lcsc) · Ray 1d ago
tps53667rtat-hero.glb tps53667rtat: hero GLB from the etched model (keeps the MPN mark) · Ray 1h ago
tps53667rtat-hero.overlay.json Publish 0.1.0 · Ray 1d ago
tps53667rtat.glb Publish 0.1.0 · Ray 1d ago
tps53667rtat.kicad_mod Publish 0.1.0 · Ray 1d ago
tps53667rtat.kicad_sym Publish 0.1.0 · Ray 1d ago
tps53667rtat.lbr Publish 0.1.0 · Ray 1d ago
tps53667rtat.step Publish 0.1.0 · Ray 1d ago

TPS53667RTAT

Texas Instruments · DC-DC Converters · WQFN-40-EP(6x6)

TPS53667RTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OCL-R input A resistor to GND and the voltage on this pin select one of 16 per-phase OCL levels and one of four RAMP levels, latched when V3R3 powers up.
2 IMON output Analog current monitor output; the digitized IMON value is compared against OC_FAULT_LIMIT (1.25× IMAX by default) for overcurrent protection.
3 CSP1 input Positive current-sense input to be connected to the IOUT pin of a TI smart power stage (e.g. CSD9549x), with recommended range −0.1 V to 2.5 V.
4 CSP2 input Positive current-sense input to be connected to the IOUT pin of a TI smart power stage; tie to V3R3 to disable this phase, with recommended range −0.1 V to 2.5 V.
5 CSP3 input Positive current-sense input to be connected to the IOUT pin of a TI smart power stage; tie to V3R3 to disable this phase, with recommended range −0.1 V to 2.5 V.
6 CSP4 input Positive current-sense input to be connected to the IOUT pin of a TI smart power stage; tie to V3R3 to disable this phase, with recommended range −0.1 V to 2.5 V.
7 CSP5 input Positive current-sense input to be connected to the IOUT pin of a TI smart power stage; tie to V3R3 to disable this phase, with recommended range −0.1 V to 2.5 V.
8 CSP6 input Positive current-sense input to be connected to the IOUT pin of a TI smart power stage; tie to V3R3 to disable this phase, with recommended range −0.1 V to 2.5 V.
9 VSP input Positive input of the remote voltage-sense amplifier, connected directly to the load, with recommended range −0.1 V to 2.5 V.
10 VSN input Negative input of the remote voltage-sense amplifier, connected directly to the load ground, with recommended range −0.1 V to 0.1 V.
11 COMP output Output of the gM error amplifier; resistors and capacitors between this pin and VREF set the compensation, with recommended maximum of 5.5 V.
12 ISUM output A resistor from this pin to VREF sets the droop (per the datasheet relation with the number of phases n), with recommended maximum of 3.5 V.
13 VREF power_out 1.7-V, 500-µA LDO reference output; bypass to GND with a 0.33-µF ceramic capacitor.
14 V3R3 power_out 3.3-V LDO output; bypass to GND with a ceramic capacitor of 1 µF or larger, with recommended range −0.1 V to 3.5 V.
15 V5 power_in 5-V power input for all internal analog circuits, with recommended range 4.5 V to 5.5 V; bypass to GND with a ceramic capacitor of 1 µF or larger.
16 VIN power_in Input voltage supply, also sensed for on-time control and input UVLO, with recommended range 4.5 V to 17 V (12 V nominal).
17 GND power_in Ground pin of the controller.
18 VR_RDY output Open-drain power-good output, typically pulled up to V3R3 through a resistor of 3 kΩ or larger.
19 VR_HOT output Open-drain, active-low thermal flag output, typically pulled up to V3R3 through a resistor of 3 kΩ or larger; leave floating if not used.
20 GND power_in Connect to GND; the datasheet notes this is not the IC ground pin.
21 RESET input Reset input; if held low for more than 1000 ns the controller pulls the output voltage to the VBOOT level, with recommended range −0.1 V to 3.5 V.
22 GND power_in Connect to GND; the datasheet notes this is not the IC ground pin.
23 ENABLE input VR enable input with 1-V I/O level and 100-ns debounce, with recommended range −0.1 V to 3.5 V.
24 PMB_CLK input I²C PMBus clock input supporting 3.3-V and 1.8-V logic levels, with recommended range −0.1 V to 3.5 V.
25 PMB_ALERT output Open-drain I²C PMBus interrupt line supporting 3.3-V and 1.8-V logic levels.
26 PMB_DIO bidirectional I²C PMBus digital data I/O line supporting 3.3-V and 1.8-V logic levels, with recommended range −0.1 V to 3.5 V.
27 VR_FAULT output Open-drain VR fault indicator that goes low on high-side FET short, over-temperature, output overvoltage, or input overcurrent; typically pulled up to V3R3 through 3 kΩ or larger, and left floating if unused.
28 ADDR-TRISE input Resistor-divider strap to VREF that sets the rise slew rate (bits 2-1), the LSB of the boot voltage (bit 0), and the 4-bit PMBus address, latched at V3R3 power-up.
29 SLEW-MODE input Resistor-divider strap to VREF that sets one of 8 slew rates and the 4-bit operating mode, latched at V3R3 power-up.
30 O-USR input Resistor-divider strap to VREF that selects one of seven OSR thresholds or OFF and sets one of seven USR levels or OFF, latched at V3R3 power-up.
31 VBOOT input Resistor-divider strap to VREF that sets the 7 high bits of the 8-bit VID boot voltage (0.5 V to 2.5 V range), latched at V3R3 power-up.
32 F-IMAX input Resistor to VREF sets the switching frequency from 300 kHz to 1 MHz, and the voltage sets IMAX via an 8-bit A/D (VF-IMAX = VVREF × IMAX / 255), latched at V3R3 power-up.
33 PWM6 output PWM signal for phase 6 to the power stage, 3.3-V logic: high turns on the high-side MOSFET, low turns on the low-side MOSFET, and tri-state is 1.7 V when both are off.
34 PWM5 output PWM signal for phase 5 to the power stage, 3.3-V logic: high turns on the high-side MOSFET, low turns on the low-side MOSFET, and tri-state is 1.7 V when both are off.
35 PWM4 output PWM signal for phase 4 to the power stage, 3.3-V logic: high turns on the high-side MOSFET, low turns on the low-side MOSFET, and tri-state is 1.7 V when both are off.
36 PWM3 output PWM signal for phase 3 to the power stage, 3.3-V logic: high turns on the high-side MOSFET, low turns on the low-side MOSFET, and tri-state is 1.7 V when both are off.
37 PWM2 output PWM signal for phase 2 to the power stage, 3.3-V logic: high turns on the high-side MOSFET, low turns on the low-side MOSFET, and tri-state is 1.7 V when both are off.
38 PWM1 output PWM signal for phase 1 to the power stage, 3.3-V logic: high turns on the high-side MOSFET, low turns on the low-side MOSFET, and tri-state is 1.7 V when both are off.
39 SKIP-NVM output A resistor to GND sets pinstrap or NVM configuration mode, can connect to the FCCM pin of the power stage, and is asserted low during soft-start; recommended maximum is 3.5 V.
40 TSEN input Connect to the TAO/FAULT pin of the power stage to sense the hottest stage temperature and its fault signal; a voltage above 2.5 V is treated as a power-stage fault by default, with recommended range −0.1 V to 5.5 V.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Power Management (PMIC)
Pins 41

CAD (KiCad official)

  • Symbol: TPS53667RTAT
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: tps53667rtat-etched.step / tps53667rtat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53667rtat.step / tps53667rtat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (126 pp, sha256 994fd9ded6c778c5, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF