component
TPS53667RTAR
Public Made by Adomby adom
Texas Instruments DC-DC Controllers, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPS53667RTAR
Texas Instruments · DC-DC Controllers · WQFN-40-EP(6x6)
TPS53667RTAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OCL-R | input | A resistor to GND and the voltage level select 1 of 16 per-phase OCL levels and one of four RAMP levels, latched when V3R3 powers up. |
| 2 | IMON | output | Analog current monitor output. |
| 3 | CSP1 | input | Positive current sense input for phase 1; connect to the IOUT pin of TI smart power stages (e.g. CSD9549x). |
| 4 | CSP2 | input | Positive current sense input for phase 2; tie to V3R3 per Table 3 to disable the phase. |
| 5 | CSP3 | input | Positive current sense input for phase 3; tie to V3R3 per Table 3 to disable the phase. |
| 6 | CSP4 | input | Positive current sense input for phase 4; tie to V3R3 per Table 3 to disable the phase. |
| 7 | CSP5 | input | Positive current sense input for phase 5; tie to V3R3 per Table 3 to disable the phase. |
| 8 | CSP6 | input | Positive current sense input for phase 6; tie to V3R3 per Table 3 to disable the phase. |
| 9 | VSP | input | Positive input of the remote voltage sense amplifier; connect directly to the load. |
| 10 | VSN | input | Negative input of the remote voltage sense amplifier; connect directly to the GND of the load. |
| 11 | COMP | output | Output of the gM error amplifier; resistors and capacitors between this pin and VREF set the compensation. |
| 12 | ISUM | output | A resistor between this pin and VREF determines the droop. |
| 13 | VREF | power_out | 1.7-V, 500-µA LDO reference voltage; bypass to GND with 0.33 µF ceramic and connect to REFIN of TI smart power stages. |
| 14 | V3R3 | power_out | 3.3-V LDO output; bypass to GND with a ceramic capacitor of 1 µF or larger. |
| 15 | V5 | power_in | 5-V power input (4.5 V to 5.5 V) powering all internal analog circuits; bypass to GND with 1 µF or larger ceramic capacitor. |
| 16 | VIN | power_in | Input voltage supply, also used for input voltage sensing for on-time control and input UVLO. |
| 17 | GND | power_in | Ground pin. |
| 18 | VR_RDY | output | Open-drain power good output, typically pulled up to V3R3 through 3 kΩ or larger. |
| 19 | VR_HOT | output | Active-low open-drain thermal flag output, typically pulled up to V3R3 through 3 kΩ or larger; leave floating if not used. |
| 20 | GND | power_in | Connect this pin to GND; note this is not the IC ground pin. |
| 21 | RESET | input | Reset pin; if low for more than 1000 ns the controller pulls the output voltage to the VBOOT level. |
| 22 | GND | power_in | Connect this pin to GND; note this is not the IC ground pin. |
| 23 | ENABLE | input | VR enable input with 1-V I/O level and 100-ns debounce. |
| 24 | PMB_CLK | input | I2C PMBus clock, 3.3-V and 1.8-V logic level. |
| 25 | PMB_ALERT | output | Open-drain I2C PMBus interrupt line, 3.3-V and 1.8-V logic level. |
| 26 | PMB_DIO | bidirectional | I2C PMBus digital I/O line, 3.3-V and 1.8-V logic level. |
| 27 | VR_FAULT | output | Open-drain VR fault indicator that is LOW on failure, typically pulled up to V3R3 through 3 kΩ or larger; leave floating if not used. |
| 28 | ADDR-TRISE | input | Voltage divider to VREF; resistor to GND sets 3 bits (rise slew rate and boot voltage LSB) and the voltage sets the 4-bit PMBus address, latched when V3R3 powers up. |
| 29 | SLEW-MODE | input | Voltage divider to VREF; resistor to GND sets 1 of 8 slew rates and the voltage sets the operation modes, latched when V3R3 powers up. |
| 30 | O-USR | input | Voltage divider to VREF; resistor to GND selects 1 of 7 OSR thresholds or OFF and the voltage selects 1 of 7 USR levels or OFF, latched when V3R3 powers up. |
| 31 | VBOOT | input | Voltage divider to VREF; resistor to GND sets boot VID bits B[3:1] and the voltage sets B[7:4], latched when V3R3 powers up. |
| 32 | F-IMAX | input | Voltage divider to VREF; resistor to GND sets the operating frequency and the voltage sets IMAX (VVREF × IMAX / 255), latched at V3R3 power-up. |
| 33 | PWM6 | output | PWM signal output for phase 6. |
| 34 | PWM5 | output | PWM signal output for phase 5. |
| 35 | PWM4 | output | PWM signal output for phase 4. |
| 36 | PWM3 | output | PWM signal output for phase 3. |
| 37 | PWM2 | output | PWM signal output for phase 2. |
| 38 | PWM1 | output | PWM signal output for phase 1. |
| 39 | SKIP-NVM | output | A resistor to GND sets pinstrap or NVM configuration mode; can also connect to the FCCM pin of TI smart power stages for SKIP or FCCM operation. |
| 40 | TSEN | input | Connect to the TAO/FAULT pin of TI smart power stages to sense the highest power stage temperature and the power stage fault signal. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Power Management ICs |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN input voltage (abs max) | VIN | -0.3 | 19 | V | 5 | ||
| V5 input voltage (abs max) | V5 | -0.3 | 6 | V | 5 | ||
| TSEN input voltage (abs max) | TSEN | -0.3 | 6 | V | 5 | ||
| Logic/sense input voltage (abs max) | -0.3 | 3.6 | V | ADDR-TRISE, CSP1-6, ENABLE, F-IMAX, OCL-R, O-USR, PMB_CLK, PMB_DIO, RESET, SLEW-MODE, VBOOT, VSP | 5 | ||
| GND, VSN voltage (abs max) | -0.3 | 0.3 | V | 5 | |||
| VREF output voltage (abs max) | VREF | -0.3 | 1.8 | V | 5 | ||
| Output pins voltage (abs max) | -0.3 | 3.6 | V | IMON, ISUM, PMB_ALERT, PWM1-6, SKIP-NVM, V3R3, VR_RDY, VR_FAULT, VR_HOT | 5 | ||
| COMP voltage (abs max) | COMP | -0.3 | 6 | V | 5 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2.5 | 2.5 | kV | HBM per ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD CDM | V(ESD) | -1.5 | 1.5 | kV | CDM per JESD22-C101, all pins | 5 | |
| VIN input voltage | VIN | 4.5 | 12 | 17 | V | 6 | |
| V5 input voltage | V5 | 4.5 | 5 | 5.5 | V | 6 | |
| TSEN input voltage | TSEN | -0.1 | 5.5 | V | 6 | ||
| CSP1-6, VSP input voltage | -0.1 | 2.5 | V | 6 | |||
| ENABLE, PMB_CLK, PMB_DIO input voltage | -0.1 | 3.5 | V | 6 | |||
| V3R3 output voltage | V3R3 | -0.1 | 3.3 | 3.5 | V | 6 | |
| VREF output voltage | VREF | -0.1 | 1.72 | V | 6 | ||
| Operating free air temperature | TA | -40 | 125 | °C | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 30.6 | °C/W | RTA (QFN) 40 pins | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 14.2 | °C/W | 6 | |||
| Junction-to-board thermal resistance | RθJB | 6.9 | °C/W | 6 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 1.8 | °C/W | 6 | |||
| VIN supply current, 6-phase active | IVIN | 115 | µA | VVDAC < VVSP < VVDAC + 100 mV, ENABLE = HI | 7 | ||
| V5 supply current | IV5 | 6.1 | 7 | mA | PMBus Idle, ENABLE = HI | 7 | |
| V5 standby current | IV5SBY | 2 | 2.6 | mA | ENABLE = LO | 7 | |
| V3R3 output voltage | VV3R3 | 3.2 | 3.3 | 3.4 | V | IV3R3 = 0 A | 7 |
| V5 UVLO OK threshold | VV5UVLOH | 4.1 | 4.25 | 4.5 | V | Ramp up | 7 |
| V5 UVLO fault threshold | VV5UVLOL | 3.95 | 4.05 | 4.25 | V | Ramp down | 7 |
| VIN UVLO voltage | VVINUVLO | 6.9 | 7.25 | 7.45 | V | MFR_SPEC_16[1:0] = 01 | 7 |
| Closed loop VSP tolerance | VDAC2 | -0.6 | 0.6 | % | VR12.0: 1 V ≤ VVSP ≤ 1.52 V, IOUT = 0 A, 0 °C ≤ TA≤ 85 °C | 7 | |
| Closed loop VSP tolerance | VDAC5 | -0.8 | 0.8 | % | VR12.0: 1.0 V ≤ VVSP ≤ 1.52 V, IOUT = 0 A, -40 °C ≤ TA≤ 125 °C | 7 | |
| VREF output | VVREF | 1.685 | 1.7 | 1.717 | V | 4.5 ≤ VV5 ≤ 5.5 V, IVREF = 0 A | 7 |
| Switching frequency 500 kHz setting | fSW | 450 | 500 | 550 | kHz | VVIN = 12 V, VVSP = 1.7 V, RF-IMAX = 30 kΩ and MFR_SPEC_12[7] = 0b | 17 |
| Fixed OVP threshold (VR12.0) | VOVPF0 | 1.7 | 1.75 | 1.8 | V | ENABLE is high and (VVSP-VVSN) > VOVPH5 for 1 μs, PWM → LO | 12 |
| Over temperature protection threshold | OTPTHLD | 125 | °C | default value | 14 |
CAD (KiCad official)
- Symbol:
TPS53667RTAR - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
tps53667rtar-etched.step/tps53667rtar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps53667rtar.step/tps53667rtar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (126 pp, sha256
994fd9ded6c778c5, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).