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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS53647RTAT

Texas Instruments · AC-DC Controllers & Regulators · QFN-40-EP(6x6)

TPS53647RTAT from Texas Instruments, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OCL-R	input	Voltage divider to VREF and GND sets one of 16 per-phase overcurrent limit levels (23-72 A) and one of four ramp levels (40-200 mVp-p); device latches settings when V3R3 powers up.
2	IMON	output	Analog current monitor output generated from summed individual phase currents; output voltage VIMON = F × VREF × (total current) / (IMAX × 35kΩ).
3	CSP1	input	Positive current sense input for phase 1 from TI smart power stage (ex: CSD95372BQ5MC); connect to IOUT pin with 5 mV/A gain.
4	CSP2	input	Positive current sense input for phase 2 from TI smart power stage; tie to V3R3 pin to disable phase 2 operation.
5	CSP3	input	Positive current sense input for phase 3 from TI smart power stage; tie to V3R3 pin to disable phase 3 operation.
6	CSP4	input	Positive current sense input for phase 4 from TI smart power stage; tie to V3R3 pin to disable phase 4 operation.
7	NC	unconnected	No connection; leave pin open or pull up to V3R3 pin.
8	NC	unconnected	No connection; leave pin open or pull up to V3R3 pin.
9	VSP	input	Positive input of remote voltage sense amplifier with typical input bias current of 300 µA; connect directly to load output voltage with differential pair spacing ≤ 10 mil.
10	VSN	input	Negative input of remote voltage sense amplifier with typical input bias current of -23 µA; connect directly to load ground.
11	COMP	output	Output of gM error amplifier (gain typically 1000 µS); external resistors and capacitors connected between this pin and VREF set compensation network.
12	ISUM	output	Summed phase current output; resistor (RISUM) connected between this pin and VREF determines droop load-line (VDROOP = gM(isum) × RISUM × RCS × IOUT / 6).
13	VREF	power_out	1.7-V, 500-µA LDO reference voltage output; bypass to GND with 0.33 µF ceramic capacitor and connect to REFIN pin of TI smart power stages.
14	V3R3	power_out	3.3-V LDO output generated from V5 with startup time ~600 µs when V5 exceeds 4.25 V; bypass to GND with 1-4.7 µF ceramic capacitor.
15	V5	power_in	5-V power input for internal analog circuits with UVLO threshold 4.25 V (ok) and 4.05 V (fault) and hysteresis of 0.23 V typical; bypass to GND with 1-4.7 µF ceramic capacitor.
16	VIN	power_in	Input voltage supply (4.5-17 V range) used for input voltage sensing, on-time control, and input undervoltage lockout (UVLO) with four selectable thresholds from 4.5 V to 10.3 V.
17	GND	power_in	Ground pin; connect to ground plane with multiple vias for low impedance return path.
18	VR_RDY	output	Power good open-drain output (36-50 Ω pull-down resistance at 0.31 V) asserted low when output voltage < (VDAC - VDROOP - 207 mV) or during startup; typically pulled up to V3R3 through 3 kΩ resistor.
19	VR_HOT	output	Thermal flag open-drain output asserted low when sensed temperature exceeds TMAX threshold (110 °C default); typically pulled up to V3R3 through 3 kΩ resistor.
20	GND	power_in	Ground pin connected to GND (not IC ground); connect to GND return path.
21	RESET	input	Reset pin with logic low threshold 0.8 V and logic high threshold 1.2 V; if held low > 1000 ns, controller pulls output voltage to VBOOT level with reset delay > 1 µs.
22	GND	power_in	Ground pin; connect to ground plane.
23	ENABLE	input	VR enable pin with 1-V I/O level logic (low threshold 0.3 V, high threshold 0.8 V) and 100-ns debounce; controls device on/off operation.
24	PMB_CLK	input	I2C PMBus clock input supporting 100 kHz and 400 kHz bus speeds; compatible with 3.3-V and 1.8-V logic levels.
25	PMB_ALERT	bidirectional	I2C PMBus interrupt line with open-drain output (asserts low on faults/warnings); compatible with 3.3-V and 1.8-V logic levels and supports SMBus alert response protocol.
26	PMB_DIO	bidirectional	I2C PMBus digital I/O data line; compatible with 3.3-V and 1.8-V logic levels for PMBus serial communication.
27	VR_FAULT	output	VR fault indicator open-drain output asserted low for input overcurrent fault, over-temperature fault (>125 °C), output overvoltage fault (>VDAC + offset), or power stage fault; typically pulled up to V3R3 through 3 kΩ resistor.
28	ADDR-TRISE	input	Voltage divider to VREF pin; resistor (RADDR-TRISE) sets 3 bits for soft-start rise slew rate (1, 1/2, 1/4, 1/8 rates) and LSB of boot voltage; voltage sets 4 bits of PMBus address (16 possible addresses).
29	SLEW-MODE	input	Voltage divider to VREF pin; resistor (RSLEW-MODE) sets one of eight output voltage slew rates (0.34-2.74 mV/µs); voltage sets 4-bit operation mode bits including VR12.0/12.5, phase interleaving, dynamic phase shedding, and zero load-line.
30	O-USR	input	Voltage divider to VREF pin; resistor (RO-USR) selects one of seven overshoot reduction (OSR) thresholds (30-140 mV) or OFF; voltage sets one of seven undershoot reduction (USR) levels (20-140 mV) or OFF.
31	VBOOT	input	Voltage divider to VREF pin; resistor (RVBOOT) sets 3 bits (B[3:1]) of boot voltage VID; voltage (VVBOOT) sets 4 bits (B[7:4]); together with ADDR-TRISE bit 0 sets 7 of 8 bits of boot voltage.
32	F-IMAX	input	Voltage divider to VREF pin; resistor (RF-IMAX) sets switching frequency (300 kHz to 1 MHz); voltage (VF-IMAX) sets maximum operating current IMAX (8-bit A/D: IMAX = VF-IMAX / VVREF × 255).
33	NC	unconnected	No connection; leave pin open or pull up to V3R3 pin.
34	NC	unconnected	No connection; leave pin open or pull up to V3R3 pin.
35	PWM4	output	PWM output signal for phase 4 switching with 3.3-V logic levels; high drives high-side MOSFET on, low drives low-side MOSFET on, tri-state (1.7 V) turns both off.
36	PWM3	output	PWM output signal for phase 3 switching with 3.3-V logic levels; high drives high-side MOSFET on, low drives low-side MOSFET on, tri-state (1.7 V) turns both off.
37	PWM2	output	PWM output signal for phase 2 switching with 3.3-V logic levels; high drives high-side MOSFET on, low drives low-side MOSFET on, tri-state (1.7 V) turns both off.
38	PWM1	output	PWM output signal for phase 1 switching with 3.3-V logic levels; high drives high-side MOSFET on, low drives low-side MOSFET on, tri-state (1.7 V) turns both off.
39	SKIP-NVM	output	Configuration mode select output and SKIP/FCCM mode signal; resistor ≤20 kΩ selects pinstrap mode, ≥100 kΩ selects NVM mode; can connect to FCCM pin of TI smart power stages for skip/continuous conduction mode operation.
40	TSEN	input	Temperature sense input for highest temperature of power stages (maximum sensed: 127.9 °C); connects to TAO/FAULT pin of TI smart power stages; over-temperature fault threshold 125 °C default with 15 °C hysteresis.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-40-EP(6x6)
Category	Power Supply Chip
Pins	41

CAD (KiCad official)

Symbol: TPS53647RTAT
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: tps53647rtat-etched.step / tps53647rtat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53647rtat.step / tps53647rtat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (123 pp, sha256 2a0c7fc1d7dab847, retrieved 2026-09-22, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF