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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

TPS53632RSMR

Texas Instruments · DC-DC Controllers · VQFN-32-EP(4x4)

TPS53632RSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDA	bidirectional	Serial digital I/O line of the I2C interface; recommended input range is -0.1 V to 3.5 V.
2	VDD	power_in	3.3-V digital power input, recommended supply 3.1 V to 3.5 V, bypass to GND with a capacitor of at least 1 µF.
3	PGOOD	output	Power-good output, open-drain; recommended voltage range is -0.1 V to 3.5 V.
4	PWM1	output	PWM control for the external driver at 5-V logic level; the controller forces the tri-state level when needed.
5	PWM2	output	PWM control for the external driver at 5-V logic level; the controller forces the tri-state level when needed.
6	PWM3	output	PWM control for the external driver at 5-V logic level; the controller forces the tri-state level when needed.
7	SKIP	output	When high, the driver enters FCCM mode, otherwise DCM mode; driving the tri-state level puts the drivers into a low-power sleep mode.
8	EN	input	Enable input with 100-ns de-bounce; the regulator enters low-power mode but retains start-up settings when brought low.
9	PU	input	Pull-up to VREF through a 10-kΩ resistor.
10	FREQ-P	input	A resistor to GND sets the per-phase switching frequency; a resistor to VREF disables dynamic phase add and drop operation.
11	RAMP	input	Voltage divider to VREF with a resistor to GND sets the ramp setting voltage and can override the factory ramp setting.
12	OCP-I	bidirectional	Voltage divider to IMON; a resistor to GND (ROCP) selects one of 8 OCP levels per phase, latched at start-up.
13	IMON	output	Analog current monitor output following VIMON = ΣVISENSE × (1 + RIMON/ROCP).
14	VINTF	input	Input voltage to the interface logic; voltage can be between 1.62 V and 3.5 V.
15	SLEWA	input	Voltage sets the 3 LSBs of the I2C address and resistance to GND selects 1 of 8 slew rates; start-up slew is SLEWRATE/2, with both values latched at start-up.
16	VIN	power_in	Input voltage information for the on-time circuits via a 10-kΩ resistor; must be connected to the conversion input voltage and must not exceed 28 V.
17	CSP1	input	Positive current sense input for phase 1; connect to the most positive node of the sense resistor or DCR network, and tie to a 3.3-V supply to disable the phase.
18	CSN1	input	Negative current sense input for phase 1 with a secondary OVP comparator and soft-stop pull-down transistor; connect to the most negative sense node.
19	CSN2	input	Negative current sense input for phase 2; connect to the most negative node of the sense resistor or DCR network.
20	CSP2	input	Positive current sense input for phase 2; connect to the most positive node of the sense resistor or DCR network, and tie to a 3.3-V supply to disable the phase.
21	CSP3	input	Positive current sense input for phase 3; connect to the most positive node of the sense resistor or DCR network, and tie to a 3.3-V supply to disable the phase.
22	CSN3	input	Negative current sense input for phase 3; connect to the most negative node of the sense resistor or DCR network.
23	GFB	input	Voltage sense return; recommended range is -0.1 V to 0.1 V, tie to PCB GND with a 10-Ω resistor when the microprocessor is not populated.
24	VFB	input	Voltage sense line tied directly to the processor VOUT sense point, with resistance to GFB greater than 1 MΩ; recommended range is -0.1 V to 3.5 V.
25	DROOP	output	Error amplifier output; resistors between DROOP and VREF and between COMP and DROOP set the droop gain ADROOP = 1 + RDROOP / RCOMP.
26	COMP	input	Error amplifier summing node; resistors RCOMP (to VREF) and RDROOP (to DROOP) set the droop gain.
27	VREF	power_in	1.7-V, 500-µA reference output; bypass to GND with a 0.22-µF ceramic capacitor.
28	V5A	power_in	5-V power input for analog circuits, recommended 4.5 V to 5.5 V, connected through a resistor to the 5-V plane and bypassed with at least 1 µF ceramic.
29	GND	power_in	Analog circuit reference; tie to a quiet point on the ground plane.
30	NC	unconnected	No connect.
31	SCL	input	Serial digital clock line of the I2C interface; recommended input range is -0.1 V to 3.5 V.
32	NC	unconnected	No connect.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(4x4)
Category	Power Supply Chip
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage, PWM3, PWM2, PWM1, SKIP, V5A		-0.3		6	V		4
Input voltage, VIN	VIN	-0.3		30	V		4
Input voltage, COMP, CSP1-CSP3, CSN1-CSN3, DROOP, EN, FREQ-P, IMON, OCP-I, O-USR, RAMP, SCL, SDA, SLEWA, VDD, VFB, VINTF, VREF		-0.3		3.6	V		4
GFB voltage		-0.2		0.2	V		4
Output voltage, PGOOD	VO	-0.3		3.6	V		4
Operating junction temperature	TJ	-40		150	°C		4
Input voltage, CSN1-CSN3, CSP1-CSP3, IMON, OCP-I, O-USR, RAMP, SCL, SDA, VDD, VFB, VINTF, VREF		-0.1		3.5	V		5
Input voltage, VIN	VIN	-0.1		28	V		5
Input voltage, COMP, DROOP, EN, FREQ-P, PWM3, PWM2, PWM1, SKIP, SLEWA, V5A		-0.1		5.5	V		5
Output voltage, GFB	VO	-0.1		0.1	V		5
Output voltage, PGOOD	VO	-0.1		3.5	V		5
Operating ambient temperature	TA	-10		105	°C		5
Junction-to-ambient thermal resistance	θJA		37.2		°C/W	JEDEC high-K board, natural convection (JESD51-7)	5
Junction-to-case (top) thermal resistance	θJCtop		31.9		°C/W	Cold plate test on package top	5
Junction-to-board thermal resistance	θJB		8.1		°C/W	Ring cold plate fixture (JESD51-8)	5
Junction-to-top characterization parameter	ψJT		0.4		°C/W	Extracted from JESD51-2a simulation	5
Junction-to-board characterization parameter	ψJB		7.9		°C/W	Extracted from JESD51-2a simulation	5
Junction-to-case (bottom) thermal resistance	θJCbot		2.2		°C/W	Cold plate test on exposed (power) pad	5
V5A supply current, 3-phase operation	IV5-3P		3.6	6	mA	3-phase operation, VDAC < VVFB < (VDAC + 100 mV), EN = 'HI'	6
VDD supply current, 3-phase operation	IVDD-3P		0.2	0.8	mA	3-phase operation, VDAC < VVFB < (VDAC + 100 mV), EN = 'HI', digital buses idle	6
V5A supply current, 1-phase operation	IV5-1P		3.5	6	mA	1-phase operation, VDAC < VVFB < (VDAC + 100 mV), EN = 'HI'	6
VDD supply current, 1-phase operation	IVDD-1P		0.2	0.8	mA	1-phase operation, VDAC < VVFB < (VDAC + 100 mV), EN = 'HI', digital buses idle	6
V5A standby current	IV5STBY		125	200	µA	EN = 'LO'	6
VDD standby current	IVDDSTBY		23	40	µA	EN = 'LO'	6
VINTF supply current	IVDD-1P8		1.7	5	mA	All conditions, digital buses idle	6
V5A UVLO OK threshold	VUVLOH	4.2	4.4	4.52	V	VVFB < 200 mV, Ramp up, VVDD > 3 V, EN = 'HI', switching begins	6
V5A UVLO fault threshold	VUVLOL	4	4.2	4.35	V	Ramp down, EN = 'HI', VVDD > 3 V, VVFB = 100 mV	6
V5A fault latch reset threshold	VPOR	1.2	1.9	2.5	V	Ramp down, EN = 'HI', VVDD > 3 V; can restart if 5-V rises to VUVLOH and no other faults present	6
VDD UVLO OK threshold	V3UVLOH	2.5	2.8	3	V	VVFB < 200 mV. Ramp up, VV5A > 4.5 V, EN = 'HI', switching begins	6
VDD UVLO fault threshold	V3UVLOL	2.4	2.6	2.8	V	Ramp down, EN = 'HI', V5A > 4.5 V, VFB = 100 mV	6
VDD fault latch reset threshold	VPOR	1.2	1.9	2.5	V	Ramp down, EN = 'HI', V5A > 4.5 V; can restart if 5-V supply rises to VUVLOH and no other faults present	6
VINTF UVLO OK threshold	VINTFUVLOH	1.4	1.5	1.6	V	Ramp up, EN = 'HI', VV5A > 4.5 V, VVFB = 100 mV	6
VINTF UVLO falling threshold	VINTFUVLOL	1.3	1.4	1.5	V	Ramp down, EN = 'HI', VV5A > 4.5 V, VVFB = 100 mV	6
VFB tolerance	VDAC1	-9		9	mV	No load active, 1.36 V ≤ VVFB ≤ 1.52 V, IOUT = 0 A	6
VFB tolerance	VDAC2	-8		8	mV	No load medium, 1.0 V ≤ VVFB ≤ 1.35 V, IOUT = 0 A	6
VFB tolerance	VDAC2	-7		7	mV	No load medium, 0.5 V ≤ VVFB ≤ 0.99 V, IOUT = 0 A	6
VREF output	VVREF	1.66	1.7	1.74	V	4.5 V ≤ VV5A ≤ 5.5 V, IVREF = 0 A	6
VREF output source	VVREFSRC	-4		-3	mV	0 A ≤ IREF ≤ 500 µA, HP-2	6
VREF output sink	VVREFSNK	3		4	mV	-500 A ≤ IREF ≤ 0 A, HP-2	6
Internal VFB initial boot voltage	VVBOOT	0.99	1	1.01	V	Initial DAC boot voltage	6
GFB differential GND to GFB	VDELGND	-100		100	mV		6
OCP voltage (valley current limit)	VOCPP	3.7	7.6	11.4	mV	ROCP-I = 20 kΩ	7
OCP voltage (valley current limit)	VOCPP	6.6	10.5	14.1	mV	ROCP-I = 24 kΩ	7
OCP voltage (valley current limit)	VOCPP	10.6	14.5	18	mV	ROCP-I = 30 kΩ	7
OCP voltage (valley current limit)	VOCPP	15.4	19.5	23	mV	ROCP-I = 39 kΩ	7
OCP voltage (valley current limit)	VOCPP	21.3	25.4	29	mV	ROCP-I = 56 kΩ	7
OCP voltage (valley current limit)	VOCPP	28.4	32.5	36.2	mV	ROCP-I = 75 kΩ	7
OCP voltage (valley current limit)	VOCPP	36.3	40.5	44	mV	ROCP-I = 100 kΩ	7
OCP voltage (valley current limit)	VOCPP	45	49.3	53	mV	ROCP-I = 150 kΩ	7
CS pin input bias current	ICS	-500	0.2	500	nA	CSPx and CSNx	7
Internal current sense gain	ACSINT	5.8	6	6.2	V/V	Gain from CSPx – CSNx to PWM comparator, RSKIP = Open	7
Fixed OVP voltage	VOVPH	1.6	1.7	1.8	V	VCSN1 > VOVPH for 1 µs	7
PGOOD high threshold	VPGDH	190		245	mV	Measured at the VFB pin w/r/t VID code, device latches OFF	7
PGOOD low threshold	VPGDL	-348		-280	mV	Measured at the VFB pin w/r/t VID code, device latches OFF	7
PWMx/SKIP output low voltage	VP-S_L		0.15	0.3	V	PWMILOAD = ± 1 mA, SKIPILOAD = ± 100 µA	7
PWMx tri-state level	VPW-SKLK	1.6	1.7	1.8	V	PWMILOAD = ± 100 µA	7
Logic leakage current	IVRTTLK	-2	0.2	2	µA	VSCL = 1.8 V, VSDA = 1.8 V, VPGOOD = 3.3 V	7
I/O leakage, EN	IENH		24	40	µA	VEN = 1.8 V	7
VIN resistance	RVIN	350		600	kΩ	EN = HI	7
PGOOD low state time after EN goes low	tPG2	225	250	275	µs	Low state time after EN goes low	8

CAD (KiCad official)

Symbol: TPS53632RSMR
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
3D model files: tps53632rsmr-etched.step / tps53632rsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53632rsmr.step / tps53632rsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 bdf4d8bd7d372ccf, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF