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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

TPS53632GRSMT

Texas Instruments · DC-DC Converters · VQFN-32-EP(4x4)

TPS53632GRSMT from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDA	bidirectional	Serial digital I/O line of the I2C interface; absolute maximum range is -0.3 V to 3.6 V.
2	VDD	power_in	3.3-V digital power input, recommended 3.1 V to 3.5 V, bypassed to GND with at least 1 µF.
3	PGOOD	output	Open-drain power-good output, recommended range -0.1 V to 3.5 V.
4	NC	unconnected	No connect.
5	PWM-LO	output	PWM control for the external low-side driver at 5-V logic level; the controller forces the tri-state level when needed, with recommended range -0.1 V to 5.5 V.
6	PWM-HI	output	PWM control for the external high-side driver at 5-V logic level; the controller forces the tri-state level when needed, with recommended range -0.1 V to 5.5 V.
7	SKIP	output	When high the driver enters FCCM mode, otherwise DCM mode; driving the tri-state level puts the drivers into low-power sleep, with recommended range -0.1 V to 5.5 V.
8	EN	input	Enable input with 100-ns de-bounce; when low the regulator enters low-power mode but retains start-up settings, with recommended range -0.1 V to 5.5 V.
9	PU	passive	Pull-up to VREF through a 10-kΩ resistor.
10	FREQ-P	input	A resistor to GND sets the per-phase switching frequency, and a resistor to VREF disables dynamic phase add and drop; recommended range -0.1 V to 5.5 V.
11	RAMP	input	Voltage divider to VREF; a resistor to GND sets the ramp setting voltage and can override the factory ramp setting, with recommended range -0.1 V to 3.5 V.
12	OCP-I	bidirectional	Voltage divider to IMON whose ratio sets the IMON gain; a resistor to GND (ROCP) selects one of 8 OCP levels per phase, latched at start-up.
13	IMON	output	Analog current monitor output following VIMON = ΣVISENSE × (1 + RIMON/ROCP).
14	VINTF	power_in	Input voltage to the interface logic, which must be between 1.62 V and 3.5 V.
15	SLEWA	input	Voltage sets the 3 LSBs of the I2C address and resistance to GND selects one of 8 slew rates, both latched at start-up; recommended range -0.1 V to 5.5 V.
16	VBUS	power_in	Provides input voltage information to the on-time circuits of both converters; must not exceed 28 V.
17	CSP1	input	Positive current sense input connected to the most positive node of the sense resistor or inductor DCR network; tie CSP2 or CSP1 to a 3.3-V supply to disable the CSP2 phase.
18	CSN1	input	Negative current sense input connected to the most negative node of the sense network; it has a secondary OVP comparator and includes the soft-stop function.
19	CSN2	input	Negative current sense input for phase 2, connected to the most negative node of the sense network; it includes the soft-stop pull-down transistor.
20	CSP2	input	Positive current sense input for phase 2; tie CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the CSP2 phase.
21	PU3	power_in	Connect to the 3.3-V supply.
22	NC	unconnected	No connect.
23	GFB	input	Voltage sense return; tie to GND on the PCB through a 10-Ω resistor when the microprocessor is not populated, with absolute range -0.2 V to 0.2 V.
24	VFB	input	Voltage sense line tied directly to the processor VOUT sense point, with more than 1 MΩ between VFB and GFB and absolute range -0.3 V to 3.6 V.
25	DROOP	output	Error amplifier output; the resistor pair to VREF and to COMP sets the droop gain, ADROOP = 1 + RDROOP / RCOMP.
26	COMP	input	Error amplifier summing node; RCOMP between VREF and COMP and RDROOP between COMP and DROOP set the droop gain.
27	VREF	power_out	1.7-V, 500-µA reference, bypassed to GND with a 0.22-µF ceramic capacitor.
28	V5A	power_in	5-V analog power input, recommended 4.5 V to 5.5 V, connected through a resistor to the 5-V plane and bypassed to GND with at least 1 µF ceramic.
29	GND	power_in	Analog circuit reference; tie to a quiet point on the ground plane.
30	NC	unconnected	No connect.
31	SCL	input	Serial digital clock line of the I2C interface; absolute range -0.3 V to 3.6 V.
32	NC	unconnected	No connect.
33	PAD	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(4x4)
Category	Power Management (PMIC)
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage V5A	VI	-0.3		6	V		4
Input voltage VBUS	VI	-0.3		30	V		4
Input voltage VDD	VI	-0.3		3.6	V		4
Input voltage (COMP, CSP1, CSP2, CSN1, CSN2, DROOP, EN, FREQ-P, IMON, OCP-I, O-USR, RAMP, SCL, SDA, SLEWA, VFB, VINTF, VREF)	VI	-0.3		3.6	V		4
Input voltage GFB	VI	-0.2		0.2	V		4
Output voltage PGOOD	VO	-0.3		3.6	V		4
Output voltage PWM-LO, PWM-HI, SKIP	VO	-0.3		6	V		4
Operating junction temperature	TJ	-40		150	°C		4
Storage temperature	Tstg			150	°C		4
Input voltage V5A	VI	4.5		5.5	V		5
Input voltage VBUS	VI	-0.1		28	V		5
Input voltage VDD	VI	3.1		3.5	V		5
Input voltage (CSN1, CSN2, CSP1, CSP2, IMON, OCP-I, O-USR, RAMP, SCL, SDA, VFB, VINTF, VREF)	VI	-0.1		3.5	V		5
Input voltage (COMP, DROOP, EN, FREQ-P, SLEWA)	VI	-0.1		5.5	V		5
Output voltage GFB	VO	-0.1		0.1	V		5
Output voltage PGOOD	VO	-0.1		3.5	V		5
Output voltage (PWM-LO, PWM-HI, SKIP)	VO	-0.1		5.5	V		5
Operating ambient temperature	TA	-10		105	°C		5
V5A supply current	IV5-3P	3.6		6	mA	VDAC < VVFB < (VDAC + 100 mV), EN = 'HI'	6
VDD supply current	IVDD-3P	0.2		0.8	mA	VDAC < VVFB < (VDAC + 100 mV), EN = 'HI', digital buses idle	6
V5A standby current	IV5STBY	125		200		EN = 'LO'	6
VDD standby current	IVDDSTBY	23		40	µA	EN = 'LO'	6
VINTF supply current	IVDD-1P8	1.7		5		All conditions, digital buses idle	6
V5A UVLO OK threshold	VUVLOH	4.2	4.4	4.52	V	VVFB < 200 mV, Ramp up, VVDD > 3 V, EN = 'HI', switching begins.	6
V5A UVLO fault threshold	VUVLOL	4	4.2	4.35	V	Ramp down, EN = 'HI', VVDD > 3 V, VVFB = 100 mV, restart if 5-V falls below VPOR then rises > VUVLOH, or EN is toggled w/ VV5A > VUVLOH	6
V5A fault latch reset threshold	VPOR	1.2	1.9	2.5	V	Ramp down, EN = 'HI', VVDD > 3 V. Can restart if 5-V rises to VUVLOH and no other faults present.	6
VDD UVLO OK threshold	V3UVLOH	2.5	2.8	3	V	VVFB < 200 mV. Ramp up, VV5A > 4.5 V, EN = 'HI', Switching begins.	6
VDD UVLO fault threshold	V3UVLOL	2.4	2.6	2.8	V	Ramp down, EN = 'HI', V5A > 4.5V, VFB = 100 mV, restart if 5-V dips below VPOR then rises > VUVLOH or EN is toggled with 5 V > VUVLOH	6
VDD fault latch reset threshold	VPOR	1.2	1.9	2.5	V	Ramp down, EN = 'HI', VV5A > 4.5 V, can restart if 5-V supply rises to VUVLOH and no other faults present.	6
VINTF UVLO OK	VINTFUVLOH	1.4	1.5	1.6	V	Ramp up, EN = 'HI', VV5A > 4.5 V, VVFB = 100 mV	6
VINTF UVLO falling	VINTFUVLOL	1.3	1.4	1.5	V	Ramp down, EN = 'HI', VV5A > 4.5 V, VVFB = 100 mV	6
VFB tolerance (no load active)	VDAC1	-9		9		No load active, 1.36 V ≤ VVFB ≤ 1.52 V, IOUT = 0 A	6
VFB tolerance (no load medium, 1.0 V to 1.35 V)	VDAC2	-8		8		No load medium, 1.0 V ≤ VVFB ≤ 1.35 V, IOUT = 0 A	6
VFB tolerance (no load medium, 0.5 V to 0.99 V)	VDAC2	-7		7		No load medium, 0.5 V ≤ VVFB ≤ 0.99 V, IOUT = 0 A	6
VREF output	VVREF	1.66	1.7	1.74	V	4.5 V ≤ VV5A ≤ 5.5 V, IVREF = 0 A	6
VREF output source	VVREFSRC	-4		-3	mV	0 A ≤ IREF ≤ 500 µA, HP-2	6
VREF output sink	VVREFSNK	3		4	mV	–500 µA ≤ IREF ≤ 0 A, HP-2	6
Internal VFB initial boot voltage	VVBOOT	0.99	1	1.01	V	Initial DAC boot voltage	6
GFB differential GND to GFB	VDELGND	-100		100	mV		6
OCP voltage (valley current limit), ROCP-I = 20 kΩ	VOCPP	3.7	7.6	11.4	mV	ROCP-I = 20 kΩ	7
OCP voltage (valley current limit), ROCP-I = 24 kΩ	VOCPP	6.6	10.5	14.1	mV	ROCP-I = 24 kΩ	7
OCP voltage (valley current limit), ROCP-I = 30 kΩ	VOCPP	10.6	14.5	18	mV	ROCP-I = 30 kΩ	7
OCP voltage (valley current limit), ROCP-I = 39 kΩ	VOCPP	15.4	19.5	23	mV	ROCP-I = 39 kΩ	7
OCP voltage (valley current limit), ROCP-I = 56 kΩ	VOCPP	21.3	25.4	29	mV	ROCP-I = 56 kΩ	7
OCP voltage (valley current limit), ROCP-I = 75 kΩ	VOCPP	28.4	32.5	36.2	mV	ROCP-I = 75 kΩ	7
OCP voltage (valley current limit), ROCP-I = 100 kΩ	VOCPP	36.3	40.5	44	mV	ROCP-I = 100 kΩ	7
OCP voltage (valley current limit), ROCP-I = 150 kΩ	VOCPP	45	49.3	53	mV	ROCP-I = 150 kΩ	7
CS pin input bias current	ICS	-500	0.2	500	nA	CSPx and CSNx	7
Error amplifier source current	IEA_SR	1			mA	IDROOP, VVFB = VDAC + 50 mV, RCOMP = 1 kΩ	7
Error amplifier sink current	IEA_SK			-1	mA	IDROOP, VVFB = VDAC – 50mV, RCOMP = 1 kΩ	7
Internal current sense gain	ACSINT	5.8	6	6.2	V/V	Gain from CSPx – CSNx to PWM comparator, RSKIP = Open	7
Soft-stop transistor resistance	RSFTSTP	100		200	Ω	Connected to CSN1	7
VIN resistance (EN = HI)	RVIN	350		600	kΩ	EN = HI	7
Fixed OVP voltage	VOVPH	1.6	1.7	1.8	V	VCSN1 > VOVPH for 1 µs	7
PGOOD high threshold	VPGDH	190		245	mV	Measured at the VFB pin w/r/t VID code, device latches OFF	7
PGOOD low threshold	VPGDL	-348		-280	mV	Measured at the VFB pin w/r/t VID code, device latches OFF	7
PWMx/SKIP low output voltage	VP-S_L	0.15		0.3	V	PWMILOAD = ± 1 mA, SKIPILOAD = ± 100 µA	7
PWMx/SKIP high output voltage	VP-S_H	4.2			V	PWMILOAD = ± 1 mA, SKIPILOAD = ± 100 µA	7
Pull-down resistance (VSDA)	RVRTTL	4		15	Ω	VSDA = 0.31	7
Pull-down resistance (VPGOOD)	RVRPG	36		50	Ω	VPGOOD= 0.31	7
Logic leakage current	IVRTTLK	-2	0.2	2	µA	VSCL= 1.8 V, VSDA = 1.8 V, VPGOOD = 3.3 V	7
Low-level input voltage	VIL			0.6	V	SCL, SDA; VVINTF = 1.8 V	7
High-level input voltage	VIH	1.2			V	SCL, SDA; VVINTF = 1.8 V	7
I/O leakage, EN leakage current	IENH	24		40	µA	VEN = 1.8 V	7
PWMx/SKIP H-L transition time	tP-S_H-L	7		20	ns	10% to 90%, both edges	8
PGOOD low state time after EN goes low	tPG2	225	250	275	µs	Low state time after EN goes low.	8
Thermal resistance, junction-to-ambient	RθJA		37.2		°C/W		5
Thermal resistance, junction-to-case (top)	RθJCtop		31.9		°C/W		5
Thermal resistance, junction-to-board	RθJB		8.1		°C/W		5
Junction-to-top characterization parameter	RψJT		0.4		°C/W		5
Junction-to-board characterization parameter	RψJB		7.9		°C/W		5
Thermal resistance, junction-to-case (bottom)	RθJCbot		2.2		°C/W		5

CAD (KiCad official)

Symbol: TPS53632GRSMT
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
3D model files: tps53632grsmt-etched.step / tps53632grsmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53632grsmt.step / tps53632grsmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 2763a5aa2352d309, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF