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TPS53219ARGTT

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Texas Instruments Power Management - Specialized, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps53219argttfactory-2.0.0extractor-text

Verified TPS53219ARGTT

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS53219ARGTT · VQFN-16-EP(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 36-page datasheet
  • ✓distributor: lcsc C2869995, digikey 296-TPS53219ARGTTTR-ND, mouser 595-TPS53219ARGTT
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-kfxu9n21/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps53219argtt.kicad_sym✓ tps53219argtt.kicad_mod✓ tps53219argtt.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers tps53219argtt: viewers · Ray 2h ago
package.json Publish 0.1.0 · Ray 2h ago
page.json Set visibility: public · Ray 2h ago
README.md Publish 0.1.0 · Ray 2h ago
tps53219argtt-etched.glb Publish 0.1.0 · Ray 2h ago
tps53219argtt-etched.step tps53219argtt: factory component page (tier=mfr) · Ray 2h ago
tps53219argtt-hero.glb tps53219argtt: hero GLB from the etched model (keeps the MPN mark) · Ray 2h ago
tps53219argtt-hero.overlay.json Publish 0.1.0 · Ray 2h ago
tps53219argtt.glb Publish 0.1.0 · Ray 2h ago
tps53219argtt.kicad_mod Publish 0.1.0 · Ray 2h ago
tps53219argtt.kicad_sym Publish 0.1.0 · Ray 2h ago
tps53219argtt.lbr Publish 0.1.0 · Ray 2h ago
tps53219argtt.step Publish 0.1.0 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray 2h ago

TPS53219ARGTT

Texas Instruments · Power Management - Specialized · VQFN-16-EP(3x3)

TPS53219ARGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TRIP input Overcurrent-limit (OCL) threshold setting pin; 10 µA at room temperature with 4700 ppm/°C is sourced, giving VOCL = VTRIP/8 with VTRIP ≤ 3 V and VOCL ≤ 375 mV.
2 EN input Enable pin; place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V.
3 VFB input Output feedback input; connect this pin to VOUT through a resistor divider.
4 RF input Switching frequency selection; a resistor to GND or VREG selects the frequency per Table 2, detected and stored at start-up.
5 MODE input Soft-start and skip/CCM selection; a resistor selects soft-start time per Table 1, detected and stored into internal register at start-up.
6 VDD power_in Controller power supply input with an input range of 4.5 V to 25 V.
7 GND power_in Ground pin for the internal analog circuitry; connect to the GND plane at a single point.
8 PGND power_in Power ground; connect to the GND plane.
9 VREG power_out 6.2-V LDO output supplying internal analog and driver circuitry.
10 VDRV input Gate drive supply voltage input; connect to VREG when using the LDO output as the gate drive supply.
11 DRVL output Synchronous MOSFET driver output referenced to PGND, with gate drive voltage defined by the VDRV voltage.
12 SW power_out Output of converted power; connect this pin to the output inductor.
13 DRVH output High-side MOSFET driver output referenced to the floating SW node, with gate drive defined by the voltage across the VBST-to-SW bootstrap capacitor.
14 VBST power_in Supply input for the high-side gate driver (boost terminal); connect a capacitor from this pin to the SW node, internally connected to VREG through the bootstrap MOSFET switch.
15 NC unconnected No connection.
16 PGOOD output Open-drain power-good flag that releases after a 1-ms start-up delay once VFB is within limits and goes low after a 2-µs delay when VFB goes out of limits.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VBST VBST -0.3 37 V 4
Input voltage VBST (ref. SW) VBST -0.3 7 V Voltage values are with respect to the SW terminal 4
Input voltage VDD VDD -0.3 28 V 4
Input voltage SW SW -2 30 V DC 4
Input voltage SW pulse SW -7 V Pulse <20ns, E = 5 µJ 4
Input voltage VDRV, EN, TRIP, VFB, RF, MODE -0.3 7 V 4
Output voltage DRVH DRVH -2 37 V 4
Output voltage DRVH (ref. SW) DRVH -0.3 7 V Voltage values are with respect to the SW terminal 4
Output voltage DRVL, VREG -0.5 7 V 4
Output voltage PGOOD PGOOD -0.3 7 V 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -55 150 °C 4
Input voltage VBST VBST -0.1 34.5 V 4
Input voltage VDD VDD 4.5 25 V 4
Input voltage SW SW -1 28 V 4
Input voltage VBST (ref. SW) VBST -0.1 6.5 V 4
Input voltage EN, TRIP, VFB, RF, VDRV, MODE -0.1 6.5 V 4
Output voltage DRVH DRVH -1 34.5 V 4
Output voltage DRVH (ref. SW) DRVH -0.1 6.5 V 4
Output voltage DRVL, VREG -0.3 6.5 V 4
Output voltage PGOOD PGOOD -0.1 6.5 V 4
Operating free-air temperature TA -40 85 °C 4
VFB regulation voltage VVFB 597 600 603 mV TA = 25°C 5
VFB regulation voltage VVFB 595.2 600 604.8 mV 0°C ≤ TA≤ 85°C 5
VFB regulation voltage VVFB 594 600 606 mV -40°C ≤ TA≤ 85°C 5
VDD supply current IVDD 420 590 µA VDD current, TA = 25°C, No Load, VEN = 5 V, VVFB = 0.630 V 5
DRVH resistance source RDRVH 1.5 3 Ω Source, IDRVH = -50 mA 5
DRVH resistance sink RDRVH 0.7 1.8 Ω Sink, IDRVH = 50 mA 5
DRVL resistance source RDRVL 1 2.2 Ω Source, IDRVL = -50 mA 5
DRVL resistance sink RDRVL 0.5 1.2 Ω Sink, IDRVL = 50 mA 5
Dead time DRVH-off to DRVL-on tDEAD 7 17 30 ns 5
Dead time DRVL-off to DRVH-on tDEAD 10 22 35 ns 5
LDO output voltage VVREG 5.76 6.2 6.67 V 0 mA ≤ IVREG ≤ 50 mA 5
Forward voltage VREG-VBST VFBST 0.1 0.2 V VVREG-VBST, IF = 10 mA, TA = 25°C 5
VBST leakage current IVBSTLK 0.01 1.5 µA VVBST = 23 V, VSW = 17 V, TA = 25°C 5
Minimum off-time tOFF(min) 150 260 400 ns TA = 25°C 5
PG threshold PG in from lower VTHPG 92.5 96 98.5 % PG in from lower 6
PG threshold PG in from higher VTHPG 108 111 114 % PG in from higher 6
EN voltage threshold enable VEN 1.8 V -40°C ≤ TA≤ 85°C 6
Switching frequency fSW 200 250 300 kHz RRF = 0 Ω to GND, TA = 25°C 6
Switching frequency fSW 350 400 450 kHz RRF = 619 kΩ to GND, TA = 25°C 6
Switching frequency fSW 450 500 550 kHz RRF = Open, TA = 25°C 6
Switching frequency fSW 880 970 1070 kHz RRF = 0 Ω to VREG, TA = 25°C 6
VO discharge current IDischg 5 13 mA VEN = 0 V, VSW = 0.5 V 6
TRIP source current ITRIP 9 10 11 µA VTRIP = 1 V, TA = 25°C 6
Current limit threshold VOCL 355 375 395 mV VTRIP = 3 V 6
Current limit threshold VOCL 185 200 215 mV VTRIP = 1.6 V 6
Negative current limit threshold VOCLN -406 -375 -355 mV VTRIP = 3 V 6
Negative current limit threshold VOCLN -215 -200 -185 mV VTRIP = 1.6 V 6
Auto zero cross adjustable range Positive VAZC(adj) 3 15 mV Positive 6
Auto zero cross adjustable range Negative VAZC(adj) -15 -3 mV Negative 6
OVP trip threshold voltage VOVP 115 120 125 % OVP detect 6
Output UVP trip threshold voltage VUVP 65 70 75 % UVP detect 6
Output UVP enable delay time from EN to UVP workable tUVP(en) 2 2.55 3 ms RMODE = 39 kΩ 6
VREG UVLO threshold wake up VUVVREG 4 4.18 4.5 V Wake up 6
Thermal shutdown threshold TSDN 145 °C Shutdown temperature 6
TRIP current temp. coef. TCITRIP 4700 ppm/°C TA = 25°C 6
Junction-to-ambient thermal resistance RθJA 51.3 °C/W 5
Junction-to-board thermal resistance RθJB 20.1 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 6 °C/W 5

CAD (KiCad official)

  • Symbol: TPS53219ARGTT
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps53219argtt-etched.step / tps53219argtt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53219argtt.step / tps53219argtt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 2aee47feccbc24a8, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF