component
TPS53219ARGTR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, QFN-16(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS53219ARGTR
Texas Instruments · DC-DC Converters · QFN-16(3x3)
TPS53219ARGTR from Texas Instruments, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TRIP | input | OCL threshold setting pin sourcing 10 µA typical at 25°C with 4700 ppm/°C temperature compensation and 0.2 V to 3 V programmable range. |
| 2 | EN | input | Enable pin with enable threshold 1.7-1.8 V and disable threshold 0.5 V, requiring 1-kΩ series resistor if source voltage exceeds 5.5 V. |
| 3 | VFB | input | Output feedback input connected to output voltage through resistor divider and compared against 0.6 V internal reference with ±0.8% tolerance. |
| 4 | RF | input | Switching frequency selection pin connected to GND or VREG through resistor for selection of eight preset frequencies from 250 kHz to 970 kHz. |
| 5 | MODE | input | Soft-start time and operational mode selection pin with four selectable soft-start times from 0.7 ms to 5.6 ms. |
| 6 | VDD | power_in | Power supply input with operating range 4.5 V to 25 V and typical quiescent current of 420-590 µA at no load condition. |
| 7 | GND | power_in | Analog ground reference pin for internal circuitry, must be connected to GND plane at single point. |
| 8 | PGND | power_in | Power ground pin for gate drivers and MOSFET source connections, connected to GND plane. |
| 9 | VREG | power_out | 6.2 V LDO regulator output providing 5.76-6.67 V over 0-50 mA output current range for internal and gate driver supply. |
| 10 | VDRV | power_in | Gate drive supply voltage input accepting 4.5 V to 6.5 V from external source or connected to VREG. |
| 11 | DRVL | output | Low-side MOSFET gate driver output with 0.5-1.2 Ω on-resistance and 10-35 ns dead-time delay to DRVH. |
| 12 | SW | power_out | Synchronous buck converter output node connecting the drain of low-side MOSFET to high-side MOSFET drain and output inductor. |
| 13 | DRVH | output | High-side floating MOSFET gate driver output with 0.7-1.8 Ω on-resistance, bootstrap powered between VBST and SW nodes. |
| 14 | VBST | power_out | Bootstrap supply pin for high-side gate driver with external capacitor connection from VBST to SW node, internally supplied from VREG. |
| 15 | NC | unconnected | No connection pin. |
| 16 | PGOOD | tri_state | Open-drain power-good output flag with 1-ms startup delay rising when output within specified voltage band and 2-µs delay falling outside band. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
TPS53219ARGTR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps53219argtr-etched.step/tps53219argtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps53219argtr.step/tps53219argtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
2aee47feccbc24a8, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).