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TPS53127RGER
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+61@@ -0,0 +1,61 @@+# TPS53127RGER++**Texas Instruments** · DC-DC Converters · VQFN-24-EP(4x4)++TPS53127RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VO1 | input | Output voltage input for VO1 on-time adjustment and output discharge; connect directly to the output voltage. |+| 2 | VFB1 | input | D-CAP2 feedback input for channel 1; connect to the output voltage through a resistor divider. |+| 3 | GND | power_in | Signal ground; connect to PGND1, PGND2 and system ground at a single point. |+| 4 | SS1 | output | Soft-start programming pin for channel 1; connect a capacitor from SS1 to GND to set the soft-start time. |+| 5 | VFB2 | input | D-CAP2 feedback input for channel 2; connect to the output voltage through a resistor divider. |+| 6 | VO2 | input | Output voltage input for VO2 on-time adjustment and output discharge; connect directly to the output voltage. |+| 7 | EN2 | input | Enable input for channel 2; pull high to enable the SMPS. |+| 8 | VBST2 | power_in | Supply input for the channel 2 high-side NFET driver; bypass to SW2 with a high-quality 0.1-µF ceramic capacitor. |+| 9 | DRVH2 | output | High-side N-channel MOSFET gate driver output for channel 2, switching between SW2 (OFF) and VBST2 (ON). |+| 10 | SW2 | bidirectional | Channel 2 switch node connection for the high-side driver and the over-current comparator. |+| 11 | DRVL2 | output | Low-side N-channel MOSFET gate driver output for channel 2, switching between PGND2 (OFF) and VREG5 (ON). |+| 12 | PGND2 | power_in | Power ground for the channel 2 low-side driver and over-current comparator; connect strongly to PGND1 and GND near the IC. |+| 13 | TRIP2 | input | Over-current threshold programming pin; connect to GND with a resistor to set the low-side RDS(ON) current limit. |+| 14 | SS2 | output | Soft-start programming pin for channel 2; connect a capacitor from SS2 to GND to set the soft-start time. |+| 15 | V5FILT | power_in | 5-V supply input for the control circuitry except the MOSFET drivers; bypass to GND with at least 1.0-µF ceramic capacitor and connected to VREG5 via an internal 10-Ω resistor. |+| 16 | VREG5 | power_out | Output of the 5-V linear regulator and supply for the MOSFET drivers; bypass to GND with at least 4.7-µF ceramic capacitor. |+| 17 | VIN | power_in | Supply input for the 5-V linear regulator; bypass to GND with at least 0.1-µF high-quality ceramic capacitor. |+| 18 | TRIP1 | input | Over-current threshold programming pin; connect to GND with a resistor to set the low-side RDS(ON) current limit. |+| 19 | PGND1 | power_in | Power ground for the channel 1 low-side driver and over-current comparator; connect strongly to PGND2 and GND near the PGND2 IC. |+| 20 | DRVL1 | output | Low-side N-channel MOSFET gate driver output for channel 1, switching between PGND1 (OFF) and VREG5 (ON). |+| 21 | SW1 | bidirectional | Channel 1 switch node connection for the high-side driver and the over-current comparator. |+| 22 | DRVH1 | output | High-side N-channel MOSFET gate driver output for channel 1, switching between SW1 (OFF) and VBST1 (ON). |+| 23 | VBST1 | power_in | Supply input for the channel 1 high-side NFET driver; bypass to SW1 with a high-quality 0.1-µF ceramic capacitor. |+| 24 | EN1 | input | Enable input for channel 1; pull high to enable the SMPS. |+| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24-EP(4x4) |+| Category | Power Management (PMIC) |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `TPS53127RGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `tps53127rger-etched.step` / `tps53127rger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps53127rger.step` / `tps53127rger.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps53127) (33 pp, sha256 `d7c5b2760d0a2f0e`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps53127rger-datasheet.pdf)
page.jsonadded+303@@ -0,0 +1,303 @@+{+ "slug": "tps53127rger",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps53127rger",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps53127rger.kicad_sym",+ "tps53127rger.kicad_mod",+ "tps53127rger.glb",+ "tps53127rger.step",+ "tps53127rger.lbr",+ "docs/hero.png",+ "docs/tps53127rger-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps53127rger-hero.glb",+ "tps53127rger-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS53127RGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24-EP(4x4)",+ "pin_count": 25,+ "category": "Power Management (PMIC)",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps53127",+ "parts": {+ "symbol": "tps53127rger.kicad_sym",+ "footprint": "tps53127rger.kicad_mod",+ "model_3d": "tps53127rger-hero.glb",+ "model_3d_plain": "tps53127rger.glb",+ "model_3d_step": "tps53127rger-etched.step",+ "model_3d_step_plain": "tps53127rger.step",+ "lbr": "tps53127rger.lbr"+ },+ "distributor_links": {+ "lcsc": "C2864624",+ "digikey": "296-TPS53127RGERTR-ND",+ "mouser": "595-TPS53127RGER"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:33:04Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-TPS53127RGERTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS53127RGER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VO1",+ "type": "input",+ "description": "Output voltage input for VO1 on-time adjustment and output discharge; connect directly to the output voltage."+ },+ {+ "number": "2",+ "name": "VFB1",+ "type": "input",+ "description": "D-CAP2 feedback input for channel 1; connect to the output voltage through a resistor divider."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground; connect to PGND1, PGND2 and system ground at a single point."+ },+ {+ "number": "4",+ "name": "SS1",+ "type": "output",+ "description": "Soft-start programming pin for channel 1; connect a capacitor from SS1 to GND to set the soft-start time."+ },+ {+ "number": "5",+ "name": "VFB2",+ "type": "input",+ "description": "D-CAP2 feedback input for channel 2; connect to the output voltage through a resistor divider."+ },+ {+ "number": "6",+ "name": "VO2",+ "type": "input",+ "description": "Output voltage input for VO2 on-time adjustment and output discharge; connect directly to the output voltage."+ },+ {+ "number": "7",+ "name": "EN2",+ "type": "input",+ "description": "Enable input for channel 2; pull high to enable the SMPS."+ },+ {+ "number": "8",+ "name": "VBST2",+ "type": "power_in",+ "description": "Supply input for the channel 2 high-side NFET driver; bypass to SW2 with a high-quality 0.1-µF ceramic capacitor."+ },+ {+ "number": "9",+ "name": "DRVH2",+ "type": "output",+ "description": "High-side N-channel MOSFET gate driver output for channel 2, switching between SW2 (OFF) and VBST2 (ON)."+ },+ {+ "number": "10",+ "name": "SW2",+ "type": "bidirectional",+ "description": "Channel 2 switch node connection for the high-side driver and the over-current comparator."+ },+ {+ "number": "11",+ "name": "DRVL2",+ "type": "output",+ "description": "Low-side N-channel MOSFET gate driver output for channel 2, switching between PGND2 (OFF) and VREG5 (ON)."+ },+ {+ "number": "12",+ "name": "PGND2",+ "type": "power_in",+ "description": "Power ground for the channel 2 low-side driver and over-current comparator; connect strongly to PGND1 and GND near the IC."+ },+ {+ "number": "13",+ "name": "TRIP2",+ "type": "input",+ "description": "Over-current threshold programming pin; connect to GND with a resistor to set the low-side RDS(ON) current limit."+ },+ {+ "number": "14",+ "name": "SS2",+ "type": "output",+ "description": "Soft-start programming pin for channel 2; connect a capacitor from SS2 to GND to set the soft-start time."+ },+ {+ "number": "15",+ "name": "V5FILT",+ "type": "power_in",+ "description": "5-V supply input for the control circuitry except the MOSFET drivers; bypass to GND with at least 1.0-µF ceramic capacitor and connected to VREG5 via an internal 10-Ω resistor."+ },+ {+ "number": "16",+ "name": "VREG5",+ "type": "power_out",+ "description": "Output of the 5-V linear regulator and supply for the MOSFET drivers; bypass to GND with at least 4.7-µF ceramic capacitor."+ },+ {+ "number": "17",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input for the 5-V linear regulator; bypass to GND with at least 0.1-µF high-quality ceramic capacitor."+ },+ {+ "number": "18",+ "name": "TRIP1",+ "type": "input",+ "description": "Over-current threshold programming pin; connect to GND with a resistor to set the low-side RDS(ON) current limit."+ },+ {+ "number": "19",+ "name": "PGND1",+ "type": "power_in",+ "description": "Power ground for the channel 1 low-side driver and over-current comparator; connect strongly to PGND2 and GND near the PGND2 IC."+ },+ {+ "number": "20",+ "name": "DRVL1",+ "type": "output",+ "description": "Low-side N-channel MOSFET gate driver output for channel 1, switching between PGND1 (OFF) and VREG5 (ON)."+ },+ {+ "number": "21",+ "name": "SW1",+ "type": "bidirectional",+ "description": "Channel 1 switch node connection for the high-side driver and the over-current comparator."+ },+ {+ "number": "22",+ "name": "DRVH1",+ "type": "output",+ "description": "High-side N-channel MOSFET gate driver output for channel 1, switching between SW1 (OFF) and VBST1 (ON)."+ },+ {+ "number": "23",+ "name": "VBST1",+ "type": "power_in",+ "description": "Supply input for the channel 1 high-side NFET driver; bypass to SW1 with a high-quality 0.1-µF ceramic capacitor."+ },+ {+ "number": "24",+ "name": "EN1",+ "type": "input",+ "description": "Enable input for channel 1; pull high to enable the SMPS."+ },+ {+ "number": "25",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The Power PAD (exposed thermal pad) appears in the page 1 drawing but the extracted pin table gives ; Pin types are mapped to KiCad ERC classes from the datasheet's I/O column and function text. The dat; Only pages 1-4 and 20-23 of the 33-page datasheet were provided; the QFN pin table (page 3) is compl",+ "exposed pad 25 added from the footprint"+ ],+ "pages_sent": 8,+ "cost_usd": 0.0765,+ "at": "2026-10-08T16:32:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps53127",+ "pages": 33,+ "sha256": "d7c5b2760d0a2f0e",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps53127rger.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f7d256794c4147daf24dcae0554fae18510315e565ad1e239b475be7fef80d8b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps53127rger-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dee9aef0a2d313f3f58a3c11f5614a27724b41b8f8789f2ded654ec3d362823b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}