component
TPS53127RGER
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS53127RGER
Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)
TPS53127RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VO1 | input | Output voltage input for VO1 on-time adjustment and output discharge; connect directly to the output voltage. |
| 2 | VFB1 | input | D-CAP2 feedback input for channel 1; connect to the output voltage through a resistor divider. |
| 3 | GND | power_in | Signal ground; connect to PGND1, PGND2 and system ground at a single point. |
| 4 | SS1 | output | Soft-start programming pin for channel 1; connect a capacitor from SS1 to GND to set the soft-start time. |
| 5 | VFB2 | input | D-CAP2 feedback input for channel 2; connect to the output voltage through a resistor divider. |
| 6 | VO2 | input | Output voltage input for VO2 on-time adjustment and output discharge; connect directly to the output voltage. |
| 7 | EN2 | input | Enable input for channel 2; pull high to enable the SMPS. |
| 8 | VBST2 | power_in | Supply input for the channel 2 high-side NFET driver; bypass to SW2 with a high-quality 0.1-µF ceramic capacitor. |
| 9 | DRVH2 | output | High-side N-channel MOSFET gate driver output for channel 2, switching between SW2 (OFF) and VBST2 (ON). |
| 10 | SW2 | bidirectional | Channel 2 switch node connection for the high-side driver and the over-current comparator. |
| 11 | DRVL2 | output | Low-side N-channel MOSFET gate driver output for channel 2, switching between PGND2 (OFF) and VREG5 (ON). |
| 12 | PGND2 | power_in | Power ground for the channel 2 low-side driver and over-current comparator; connect strongly to PGND1 and GND near the IC. |
| 13 | TRIP2 | input | Over-current threshold programming pin; connect to GND with a resistor to set the low-side RDS(ON) current limit. |
| 14 | SS2 | output | Soft-start programming pin for channel 2; connect a capacitor from SS2 to GND to set the soft-start time. |
| 15 | V5FILT | power_in | 5-V supply input for the control circuitry except the MOSFET drivers; bypass to GND with at least 1.0-µF ceramic capacitor and connected to VREG5 via an internal 10-Ω resistor. |
| 16 | VREG5 | power_out | Output of the 5-V linear regulator and supply for the MOSFET drivers; bypass to GND with at least 4.7-µF ceramic capacitor. |
| 17 | VIN | power_in | Supply input for the 5-V linear regulator; bypass to GND with at least 0.1-µF high-quality ceramic capacitor. |
| 18 | TRIP1 | input | Over-current threshold programming pin; connect to GND with a resistor to set the low-side RDS(ON) current limit. |
| 19 | PGND1 | power_in | Power ground for the channel 1 low-side driver and over-current comparator; connect strongly to PGND2 and GND near the PGND2 IC. |
| 20 | DRVL1 | output | Low-side N-channel MOSFET gate driver output for channel 1, switching between PGND1 (OFF) and VREG5 (ON). |
| 21 | SW1 | bidirectional | Channel 1 switch node connection for the high-side driver and the over-current comparator. |
| 22 | DRVH1 | output | High-side N-channel MOSFET gate driver output for channel 1, switching between SW1 (OFF) and VBST1 (ON). |
| 23 | VBST1 | power_in | Supply input for the channel 1 high-side NFET driver; bypass to SW1 with a high-quality 0.1-µF ceramic capacitor. |
| 24 | EN1 | input | Enable input for channel 1; pull high to enable the SMPS. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN supply input voltage | VIN | 4.5 | 24 | V | 4 | ||
| V5FILT supply input voltage | V5FILT | 4.5 | 5.5 | V | 4 | ||
| VBST bootstrap voltage | VBST1, VBST2 | -0.1 | 30 | V | 4 | ||
| VBST to SW voltage | VBST1 - SW1, VBST2 - SW2 | -0.1 | 5.5 | V | 4 | ||
| Output/feedback input voltage | VFB1, VFB2, VO1, VO2 | -0.1 | 5.5 | V | 4 | ||
| TRIP input voltage | TRIP1, TRIP2 | -0.1 | 0.3 | V | 4 | ||
| Enable input voltage | EN1, EN2 | -0.1 | 24 | V | 4 | ||
| Switch node voltage | SW1, SW2 | -1.8 | 24 | V | 4 | ||
| DRVH output voltage | DRVH1, DRVH2 | -0.1 | 30 | V | 4 | ||
| DRVL, VREG5, SS output voltage | DRVL1, DRVL2, VREG5, SS1, SS2 | -0.1 | 5.5 | V | 4 | ||
| PGND voltage | PGND1, PGND2 | -0.1 | 0.1 | V | 4 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| VIN, EN input voltage absolute maximum | VIN, EN1, EN2 | -0.3 | 26 | V | 4 | ||
| VBST absolute maximum | VBST1, VBST2 | -0.3 | 32 | V | 4 | ||
| VBST to SW absolute maximum | VBST1 - SW1, VBST2 - SW2 | -0.3 | 6 | V | 4 | ||
| Low-voltage input/output absolute maximum | V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2 | -0.3 | 6 | V | 4 | ||
| SW absolute maximum | SW1, SW2 | -2 | 26 | V | 4 | ||
| DRVH absolute maximum | DRVH1, DRVH2 | -1 | 32 | V | 4 | ||
| DRVH to SW absolute maximum | DRVH1 - SW1, DRVH2 - SW2 | -0.3 | 6 | V | 4 | ||
| DRVL, VREG5, SS absolute maximum | DRVL1, DRVL2, VREG5, SS1, SS2 | -0.3 | 6 | V | 4 | ||
| PGND absolute maximum | PGND1, PGND2 | -0.3 | 0.3 | V | 4 | ||
| Operating free-air temperature absolute maximum | TA | -40 | 85 | °C | 4 | ||
| Junction temperature absolute maximum | TJ | -40 | 150 | °C | 4 | ||
| VIN supply current | IIN | 450 | 800 | μA | TA = 25°C, VREG5 tied to V5FILT, EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.8 V, SW1 = SW2 = 0.5 V | 5 | |
| VIN shutdown current | I(VINSDN) | 30 | 60 | μA | TA = 25°C, no load, EN1 = EN2 = 0 V, VREG5 = ON | 5 | |
| VFBx threshold voltage | V(VFBTHx) | 748 | 758 | 768 | mV | TA = 25°C, SWinj = OFF | 5 |
| VFBx threshold voltage | V(VFBTHx) | 746.6 | 769.4 | mV | TA = 0°C to 70°C, SWinj = OFF | 5 | |
| VFBx threshold voltage | V(VFBTHx) | 745 | 771 | mV | TA = -40°C to 85°C, SWinj = OFF | 5 | |
| VFB input current | I(VFB) | -100 | -10 | 100 | nA | VFBx = 0.8 V, TA = 25°C | 5 |
| VO discharge resistance | R(Dischg) | 40 | 80 | Ω | ENx = 0 V, VOx = 0.5 V, TA = 25°C | 5 | |
| VREG5 output voltage | V(VREG)5 | 4.6 | 5 | 5.2 | V | TA = 25°C, 5.5 V < VIN < 24 V, 0 < I(VREG5) < 10 mA | 5 |
| DRVH resistance, source | R(DRVH) | 5.5 | 11 | Ω | Source, I(DRVHx) = –100 mA | 5 | |
| DRVH resistance, sink | R(DRVH) | 2.5 | 5 | Ω | Sink, I(DRVHx) = 100 mA | 5 | |
| DRVL resistance, source | R(DRVL) | 4 | 12 | Ω | Source, I(DRVLx) = –100 mA | 5 | |
| DRVL resistance, sink | R(DRVL) | 2 | 4 | Ω | Sink, I(DRVLx) = 100 mA | 5 | |
| Internal boost diode forward voltage | V(FBST) | 0.7 | 0.8 | 0.9 | V | IF = 10 mA, TA = 25°C | 5 |
| VBST leakage current | I(VBSTLK) | 0.1 | 1 | μA | VBSTx = 29 V, SWx = 24 V, TA = 25°C | 5 | |
| SS1/SS2 charge current | I(SSC) | -2.5 | -2 | -1.5 | μA | VSS1/VSS2 = 0 V, TA = 25°C | 6 |
| ISSC temperature coefficient | TC(ISSC) | -4 | 3 | nA/°C | On the basis of 25°C | 6 | |
| SS1/SS2 discharge current | ISSD | 100 | 150 | μA | VSS1/VSS2 = 0.5 V | 6 | |
| V5FILT UVLO threshold (wake up) | V(UV5VFILT) | 3.7 | 4 | 4.3 | V | Wake up | 6 |
| TRIP source current | I(TRIP) | 8.5 | 10 | 11.5 | μA | V(TRIPx) = 0.1 V, TA = 25°C | 6 |
| OCP compensation offset | VOC(Loff) | -15 | 0 | 15 | mV | V(TRIPx-GND) = 60 mV, TA = 25°C | 6 |
| OCP compensation offset | VOC(Loff) | -20 | 20 | mV | V(TRIPx-GND) = 60 mV | 6 | |
| Current limit threshold setting range | VR(trip) | 30 | 300 | mV | V(TRIPx-GND) voltage | 6 | |
| Output OVP trip threshold | VOVP | 110 | 115 | 120 | % | OVP detect | 6 |
| Output UVP trip threshold | VUVP | 65 | 70 | 75 | % | UVP detect | 6 |
| ITRIP temperature coefficient | TC(ITRIP) | 4000 | ppm/°C | On the basis of 25°C | 6 | ||
| ENx high-level input voltage | V(ENH) | 2 | V | EN 1/2 | 6 | ||
| Thermal shutdown threshold | TSDN | 150 | °C | Shutdown temperature | 6 | ||
| DRVHx-low to DRVLx-on dead time | tD | 20 | 50 | 80 | ns | 6 | |
| DRVLx-low to DRVHx-on dead time | tD | 20 | 40 | 80 | ns | 6 | |
| Output UVP delay | tUVPDEL | 17 | 30 | 40 | µs | 6 | |
| UVP enable delay / soft-start time multiplier | tUVPEN | 1.4 | 1.7 | 2 | x (soft-start time) | 6 | |
| Output OVP propagation delay | tOVPDEL | 1.5 | µs | 6 | |||
| CH1 on time | tON1L | 165 | ns | SW1 = 12 V, VO1 = 1.8 V | 6 | ||
| CH2 on time | tON2L | 140 | ns | SW2 = 12 V, VO2 = 1.8 V | 6 | ||
| Junction-to-ambient thermal resistance (RGE) | RθJA | 35.4 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance (RGE) | RθJC(bot) | 3.8 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS53127RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps53127rger-etched.step/tps53127rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps53127rger.step/tps53127rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
d7c5b2760d0a2f0e, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).