component
TPS53119RGTR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS53119RGTR
Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)
TPS53119RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TRIP | input | OCL detection threshold setting pin, with VOCL = VTRIP / 8 where VTRIP is up to 3 V and VOCL is limited to 375 mV. |
| 2 | EN | input | Enable pin; place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V. |
| 3 | VFB | input | Output feedback input, connected to VOUT through a resistor divider. |
| 4 | RF | input | Switching frequency selection; a resistor to GND or VREG selects the frequency per Table 2, detected at start-up. |
| 5 | MODE | input | Soft-start and skip/CCM selection; a resistor selects the soft-start time per Table 1, detected at start-up. |
| 6 | VDD | power_in | Controller power supply input with an input range of 4.5 V to 25 V. |
| 7 | GND | power_in | Ground pin for the internal analog circuitry, to be connected to the GND plane at a single point. |
| 8 | PGND | power_in | Power ground, to be connected to the GND plane. |
| 9 | VREG | power_out | 6.2-V LDO output that supplies internal analog and driver circuitry. |
| 10 | VDRV | input | Gate drive supply voltage input, connected to VREG when the LDO output is used as the gate-drive supply; recommended range is -0.1 V to 6.5 V. |
| 11 | DRVL | output | Synchronous MOSFET driver output referenced to PGND, with gate drive voltage defined by VDRV. |
| 12 | SW | power_out | Output of converted power, connected to the output inductor; SW is rated -1 V to 28 V in recommended operating conditions. |
| 13 | DRVH | output | High-side MOSFET driver output referenced to the floating SW node, with gate drive voltage defined by the VBST-to-SW bootstrap capacitor. |
| 14 | VBST | power_in | Supply input for the high-side gate driver (boost terminal); connect a capacitor from this pin to SW, with 6.5 V recommended maximum relative to SW. |
| 15 | NC | unconnected | No connection. |
| 16 | PGOOD | output | Open-drain power-good flag that goes low 2 µs after VFB leaves its limits and releases after a 1-ms start-up delay. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VBST | VBST | -0.3 | 35 | V | 4 | ||
| Input voltage VBST (note 2) | VBST | -0.3 | 7 | V | Note 2: with respect to SW terminal | 4 | |
| Input voltage VDD | VDD | -0.3 | 26 | V | 4 | ||
| Input voltage SW DC | SW | -2 | 28 | V | DC | 4 | |
| Input voltage SW pulse | SW | -7 | V | Pulse < 20 ns, E = 5 µJ | 4 | ||
| Input voltage VDRV, EN, TRIP, VFB, RF, MODE | VDRV, EN, TRIP, VFB, RF, MODE | -0.3 | 7 | V | 4 | ||
| Output voltage DRVH | DRVH | -2 | 35 | V | 4 | ||
| Output voltage DRVH (note 2) | DRVH | -0.3 | 7 | V | Note 2: with respect to SW terminal | 4 | |
| Output voltage DRVL, VREG | DRVL, VREG | -0.5 | 7 | V | 4 | ||
| Output voltage PGOOD | PGOOD | -0.3 | 7 | V | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Input voltage VBST (recommended) | VBST | -0.1 | 34.5 | V | 4 | ||
| Input voltage VDD (recommended) | VDD | 4.5 | 25 | V | 4 | ||
| Input voltage SW (recommended) | SW | -1 | 28 | V | 4 | ||
| Input voltage VBST (recommended, note 1) | VBST | -0.1 | 6.5 | V | Note 1: with respect to SW terminal | 4 | |
| Input voltage EN, TRIP, VFB, RF, VDRV, MODE (recommended) | EN, TRIP, VFB, RF, VDRV, MODE | -0.1 | 6.5 | V | 4 | ||
| Output voltage DRVH (recommended) | DRVH | -1 | 34.5 | V | 4 | ||
| Output voltage DRVH (recommended, note 1) | DRVH | -0.1 | 6.5 | V | Note 1: with respect to SW terminal | 4 | |
| Output voltage DRVL, VREG (recommended) | DRVL, VREG | -0.3 | 6.5 | V | 4 | ||
| Output voltage PGOOD (recommended) | PGOOD | -0.1 | 6.5 | V | 4 | ||
| Operating free-air temperature | TA | -20 | 85 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 51.3 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 6 | °C/W | 5 | |||
| VDD supply current | IVDD | 420 | 590 | µA | VDD current, TA = 25°C, no load, VEN = 5 V, VVFB = 0.630 V | 5 | |
| VDD shutdown current | IVDDSDN | 10 | µA | VDD current, TA = 25°C, no load, VEN = 0 V | 5 | ||
| VFB regulation voltage | VVFB | 597 | 600 | 603 | mV | TA = 25°C | 5 |
| VFB regulation voltage | VVFB | 592 | 600 | 608 | mV | -20°C ≤ TA ≤ 85°C | 5 |
| DRVH resistance source | RDRVH | 1.5 | 3 | Ω | Source, IDRVH = -50 mA | 5 | |
| DRVH resistance sink | RDRVH | 0.7 | 1.8 | Ω | Sink, IDRVH = 50 mA | 5 | |
| DRVL resistance source | RDRVL | 1 | 2.2 | Ω | Source, IDRVL = -50 mA | 5 | |
| DRVL resistance sink | RDRVL | 0.5 | 1.2 | Ω | Sink, IDRVL = 50 mA | 5 | |
| Dead time DRVH-off to DRVL-on | tDEAD | 7 | 17 | 30 | ns | DRVH-off to DRVL-on | 5 |
| Dead time DRVL-off to DRVH-on | tDEAD | 10 | 22 | 35 | ns | DRVL-off to DRVH-on | 5 |
| LDO output voltage | VVREG | 5.76 | 6.2 | 6.67 | V | 0 mA ≤ IVREG ≤ 50 mA | 5 |
| LDO dropout voltage | VDO | 364 | mV | VVDD = 4.5 V, IVREG = 50 mA | 5 | ||
| Minimum off-time | tOFF(min) | 150 | 260 | 400 | ns | TA = 25°C | 5 |
| Minimum ON-time | tON(min) | 35 | ns | VIN = 17 V, VOUT = 0.6 V, RRF = 0 Ω to VREG, TA = 25°C | 5 | ||
| PG threshold, PG in from lower | VTHPG | 92.5 | 96 | 98.5 | % | PG in from lower | 6 |
| PG threshold, PG in from higher | VTHPG | 108 | 111 | 114 | % | PG in from higher | 6 |
| PG hysteresis | 2.5 | 5 | 7.8 | % | PG hysteresis | 6 | |
| PG transistor on-resistance | RPG | 15 | 30 | 50 | Ω | PG transistor on-resistance | 6 |
| PG delay after soft start | tPG(del) | 0.8 | 1 | 1.2 | ms | PG delay after soft start | 6 |
| EN voltage threshold enable | VEN | 1.8 | V | -20°C ≤ TA ≤ 85°C | 6 | ||
| EN voltage threshold disable | VEN | 0.5 | V | EN voltage threshold disable | 6 | ||
| EN input current | IEN | 1 | µA | VEN = 5 V | 6 | ||
| Switching frequency | fSW | 200 | 250 | 300 | kHz | RRF = 0 Ω to GND, TA = 25°C | 6 |
| Switching frequency | fSW | 250 | 300 | 350 | kHz | RRF = 187 kΩ to GND, TA = 25°C | 6 |
| Switching frequency | fSW | 350 | 400 | 450 | kHz | RRF = 619 kΩ to GND, TA = 25°C | 6 |
| Switching frequency | fSW | 450 | 500 | 550 | kHz | RRF = open, TA = 25°C | 6 |
| Switching frequency | fSW | 580 | 650 | 720 | kHz | RRF = 866 kΩ to VREG, TA = 25°C | 6 |
| Switching frequency | fSW | 670 | 750 | 820 | kHz | RRF = 309 kΩ to VREG, TA = 25°C | 6 |
| Switching frequency | fSW | 770 | 850 | 930 | kHz | RRF = 124 kΩ to VREG, TA = 25°C | 6 |
| Switching frequency | fSW | 880 | 970 | 1070 | kHz | RRF = 0 Ω to VREG, TA = 25°C | 6 |
| VO discharge current | IDischg | 5 | 13 | mA | VEN = 0 V, VSW = 0.5 V | 6 | |
| TRIP source current | ITRIP | 9 | 10 | 11 | µA | VTRIP = 1 V, TA = 25°C | 6 |
| Current limit threshold setting range | VTRIP | 0.2 | 3 | V | VTRIP-GND voltage | 6 | |
| Current limit threshold | VOCL | 355 | 375 | 395 | mV | VTRIP = 3 V | 6 |
| Negative current limit threshold | VOCLN | -406 | -375 | -355 | mV | VTRIP = 3 V | 6 |
CAD (KiCad official)
- Symbol:
TPS53119RGTR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps53119rgtr-etched.step/tps53119rgtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps53119rgtr.step/tps53119rgtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
a0a13063ea225718, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS53119RGTR
**Texas Instruments** · DC-DC Converters · VQFN-16-EP(3x3)
TPS53119RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TRIP | input | OCL detection threshold setting pin, with VOCL = VTRIP / 8 where VTRIP is up to 3 V and VOCL is limited to 375 mV. |
| 2 | EN | input | Enable pin; place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V. |
| 3 | VFB | input | Output feedback input, connected to VOUT through a resistor divider. |
| 4 | RF | input | Switching frequency selection; a resistor to GND or VREG selects the frequency per Table 2, detected at start-up. |
| 5 | MODE | input | Soft-start and skip/CCM selection; a resistor selects the soft-start time per Table 1, detected at start-up. |
| 6 | VDD | power_in | Controller power supply input with an input range of 4.5 V to 25 V. |
| 7 | GND | power_in | Ground pin for the internal analog circuitry, to be connected to the GND plane at a single point. |
| 8 | PGND | power_in | Power ground, to be connected to the GND plane. |
| 9 | VREG | power_out | 6.2-V LDO output that supplies internal analog and driver circuitry. |
| 10 | VDRV | input | Gate drive supply voltage input, connected to VREG when the LDO output is used as the gate-drive supply; recommended range is -0.1 V to 6.5 V. |
| 11 | DRVL | output | Synchronous MOSFET driver output referenced to PGND, with gate drive voltage defined by VDRV. |
| 12 | SW | power_out | Output of converted power, connected to the output inductor; SW is rated -1 V to 28 V in recommended operating conditions. |
| 13 | DRVH | output | High-side MOSFET driver output referenced to the floating SW node, with gate drive voltage defined by the VBST-to-SW bootstrap capacitor. |
| 14 | VBST | power_in | Supply input for the high-side gate driver (boost terminal); connect a capacitor from this pin to SW, with 6.5 V recommended maximum relative to SW. |
| 15 | NC | unconnected | No connection. |
| 16 | PGOOD | output | Open-drain power-good flag that goes low 2 µs after VFB leaves its limits and releases after a 1-ms start-up delay. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VBST | VBST | -0.3 | | 35 | V | | 4 |
| Input voltage VBST (note 2) | VBST | -0.3 | | 7 | V | Note 2: with respect to SW terminal | 4 |
| Input voltage VDD | VDD | -0.3 | | 26 | V | | 4 |
| Input voltage SW DC | SW | -2 | | 28 | V | DC | 4 |
| Input voltage SW pulse | SW | -7 | | | V | Pulse < 20 ns, E = 5 µJ | 4 |
| Input voltage VDRV, EN, TRIP, VFB, RF, MODE | VDRV, EN, TRIP, VFB, RF, MODE | -0.3 | | 7 | V | | 4 |
| Output voltage DRVH | DRVH | -2 | | 35 | V | | 4 |
| Output voltage DRVH (note 2) | DRVH | -0.3 | | 7 | V | Note 2: with respect to SW terminal | 4 |
| Output voltage DRVL, VREG | DRVL, VREG | -0.5 | | 7 | V | | 4 |
| Output voltage PGOOD | PGOOD | -0.3 | | 7 | V | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -55 | | 150 | °C | | 4 |
| Input voltage VBST (recommended) | VBST | -0.1 | | 34.5 | V | | 4 |
| Input voltage VDD (recommended) | VDD | 4.5 | | 25 | V | | 4 |
| Input voltage SW (recommended) | SW | -1 | | 28 | V | | 4 |
| Input voltage VBST (recommended, note 1) | VBST | -0.1 | | 6.5 | V | Note 1: with respect to SW terminal | 4 |
| Input voltage EN, TRIP, VFB, RF, VDRV, MODE (recommended) | EN, TRIP, VFB, RF, VDRV, MODE | -0.1 | | 6.5 | V | | 4 |
| Output voltage DRVH (recommended) | DRVH | -1 | | 34.5 | V | | 4 |
| Output voltage DRVH (recommended, note 1) | DRVH | -0.1 | | 6.5 | V | Note 1: with respect to SW terminal | 4 |
| Output voltage DRVL, VREG (recommended) | DRVL, VREG | -0.3 | | 6.5 | V | | 4 |
| Output voltage PGOOD (recommended) | PGOOD | -0.1 | | 6.5 | V | | 4 |
| Operating free-air temperature | TA | -20 | | 85 | °C | | 4 |
| Junction-to-ambient thermal resistance | RθJA | | 51.3 | | °C/W | | 5 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | | 6 | | °C/W | | 5 |
| VDD supply current | IVDD | | 420 | 590 | µA | VDD current, TA = 25°C, no load, VEN = 5 V, VVFB = 0.630 V | 5 |
| VDD shutdown current | IVDDSDN | | | 10 | µA | VDD current, TA = 25°C, no load, VEN = 0 V | 5 |
| VFB regulation voltage | VVFB | 597 | 600 | 603 | mV | TA = 25°C | 5 |
| VFB regulation voltage | VVFB | 592 | 600 | 608 | mV | -20°C ≤ TA ≤ 85°C | 5 |
| DRVH resistance source | RDRVH | | 1.5 | 3 | Ω | Source, IDRVH = -50 mA | 5 |
| DRVH resistance sink | RDRVH | | 0.7 | 1.8 | Ω | Sink, IDRVH = 50 mA | 5 |
| DRVL resistance source | RDRVL | | 1 | 2.2 | Ω | Source, IDRVL = -50 mA | 5 |
| DRVL resistance sink | RDRVL | | 0.5 | 1.2 | Ω | Sink, IDRVL = 50 mA | 5 |
| Dead time DRVH-off to DRVL-on | tDEAD | 7 | 17 | 30 | ns | DRVH-off to DRVL-on | 5 |
| Dead time DRVL-off to DRVH-on | tDEAD | 10 | 22 | 35 | ns | DRVL-off to DRVH-on | 5 |
| LDO output voltage | VVREG | 5.76 | 6.2 | 6.67 | V | 0 mA ≤ IVREG ≤ 50 mA | 5 |
| LDO dropout voltage | VDO | | | 364 | mV | VVDD = 4.5 V, IVREG = 50 mA | 5 |
| Minimum off-time | tOFF(min) | 150 | 260 | 400 | ns | TA = 25°C | 5 |
| Minimum ON-time | tON(min) | | | 35 | ns | VIN = 17 V, VOUT = 0.6 V, RRF = 0 Ω to VREG, TA = 25°C | 5 |
| PG threshold, PG in from lower | VTHPG | 92.5 | 96 | 98.5 | % | PG in from lower | 6 |
| PG threshold, PG in from higher | VTHPG | 108 | 111 | 114 | % | PG in from higher | 6 |
| PG hysteresis | | 2.5 | 5 | 7.8 | % | PG hysteresis | 6 |
| PG transistor on-resistance | RPG | 15 | 30 | 50 | Ω | PG transistor on-resistance | 6 |
| PG delay after soft start | tPG(del) | 0.8 | 1 | 1.2 | ms | PG delay after soft start | 6 |
| EN voltage threshold enable | VEN | 1.8 | | | V | -20°C ≤ TA ≤ 85°C | 6 |
| EN voltage threshold disable | VEN | | | 0.5 | V | EN voltage threshold disable | 6 |
| EN input current | IEN | | | 1 | µA | VEN = 5 V | 6 |
| Switching frequency | fSW | 200 | 250 | 300 | kHz | RRF = 0 Ω to GND, TA = 25°C | 6 |
| Switching frequency | fSW | 250 | 300 | 350 | kHz | RRF = 187 kΩ to GND, TA = 25°C | 6 |
| Switching frequency | fSW | 350 | 400 | 450 | kHz | RRF = 619 kΩ to GND, TA = 25°C | 6 |
| Switching frequency | fSW | 450 | 500 | 550 | kHz | RRF = open, TA = 25°C | 6 |
| Switching frequency | fSW | 580 | 650 | 720 | kHz | RRF = 866 kΩ to VREG, TA = 25°C | 6 |
| Switching frequency | fSW | 670 | 750 | 820 | kHz | RRF = 309 kΩ to VREG, TA = 25°C | 6 |
| Switching frequency | fSW | 770 | 850 | 930 | kHz | RRF = 124 kΩ to VREG, TA = 25°C | 6 |
| Switching frequency | fSW | 880 | 970 | 1070 | kHz | RRF = 0 Ω to VREG, TA = 25°C | 6 |
| VO discharge current | IDischg | 5 | | 13 | mA | VEN = 0 V, VSW = 0.5 V | 6 |
| TRIP source current | ITRIP | 9 | 10 | 11 | µA | VTRIP = 1 V, TA = 25°C | 6 |
| Current limit threshold setting range | VTRIP | 0.2 | | 3 | V | VTRIP-GND voltage | 6 |
| Current limit threshold | VOCL | 355 | 375 | 395 | mV | VTRIP = 3 V | 6 |
| Negative current limit threshold | VOCLN | -406 | -375 | -355 | mV | VTRIP = 3 V | 6 |
## CAD (KiCad official)
- Symbol: `TPS53119RGTR`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `tps53119rgtr-etched.step` / `tps53119rgtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps53119rgtr.step` / `tps53119rgtr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps53119.pdf) (37 pp, sha256 `a0a13063ea225718`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps53119rgtr-datasheet.pdf)