component
TPS51463RGER
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+61@@ -0,0 +1,61 @@+# TPS51463RGER++**Texas Instruments** · DC-DC Converters · VQFN-24-EP(4x4)++TPS51463RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Signal ground for the controller. |+| 2 | VREF | power_out | 2.0-V reference output; connect a 0.22-µF ceramic capacitor to GND. |+| 3 | COMP | output | Connect a series R-C network between COMP and the VREF pin for loop compensation. |+| 4 | SLEW | bidirectional | Programs startup and voltage-transition time via an external capacitor charged by a 10-µA current source. |+| 5 | VOUT | input | Output voltage monitor input used for regulation, power-good, OVP and UVP sensing. |+| 6 | MODE | input | Selects the switching frequency (700 kHz or 1 MHz) through the resistor connection on this pin, with a 1.8-V nominal threshold (see Table 3). |+| 7 | SW | bidirectional | Switching node output; connect to the external inductor. |+| 8 | SW | bidirectional | Switching node output; connect to the external inductor. |+| 9 | SW | bidirectional | Switching node output; connect to the external inductor. |+| 10 | SW | bidirectional | Switching node output; connect to the external inductor. |+| 11 | SW | bidirectional | Switching node output; connect to the external inductor. |+| 12 | BST | input | Bootstrap supply for the internal high-side gate driver; connect a 0.1-µF bootstrap capacitor between this pin and SW. |+| 13 | EN | input | Enable input for the SMPS; logic high is 0.8 V minimum and logic low is 0.3 V maximum. |+| 14 | VID0 | input | 2-bit VID input (with VID1) selecting the output voltage per Table 1; logic high 0.8 V minimum, logic low 0.3 V maximum. |+| 15 | VID1 | input | 2-bit VID input (with VID0) selecting the output voltage per Table 1; logic high 0.8 V minimum, logic low 0.3 V maximum. |+| 16 | PGOOD | output | Open-drain power-good output; connect a pull-up resistor (100 kΩ recommended), with 0.3 V maximum pull-down voltage at 4 mA sink. |+| 17 | V5FILT | power_in | 5-V supply for analog circuits; 4.5 V to 5.5 V range, with UVLO at about 4.3 V. |+| 18 | V5DRV | power_in | 5-V supply for the internal gate driver; 4.5 V to 5.5 V range. |+| 19 | PGND | power_in | Power ground; source terminal of the low-side power FET. |+| 20 | PGND | power_in | Power ground; source terminal of the low-side power FET. |+| 21 | PGND | power_in | Power ground; source terminal of the low-side power FET. |+| 22 | VIN | power_in | Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V. |+| 23 | VIN | power_in | Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V. |+| 24 | VIN | power_in | Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V. |+| 25 | Thermal Pad | power_in | Exposed thermal pad; connect directly to the system GND plane with multiple vias (must be soldered to the PCB). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24-EP(4x4) |+| Category | Power Management (PMIC) |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `TPS51463RGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `tps51463rger-etched.step` / `tps51463rger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps51463rger.step` / `tps51463rger.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/ds/symlink/tps51463.pdf) (27 pp, sha256 `31438a7865a64bbb`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps51463rger-datasheet.pdf)
page.jsonadded+302@@ -0,0 +1,302 @@+{+ "slug": "tps51463rger",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps51463rger",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps51463rger.kicad_sym",+ "tps51463rger.kicad_mod",+ "tps51463rger.glb",+ "tps51463rger.step",+ "tps51463rger.lbr",+ "docs/hero.png",+ "docs/tps51463rger-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps51463rger-hero.glb",+ "tps51463rger-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS51463RGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24-EP(4x4)",+ "pin_count": 25,+ "category": "Power Management (PMIC)",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/ds/symlink/tps51463.pdf",+ "parts": {+ "symbol": "tps51463rger.kicad_sym",+ "footprint": "tps51463rger.kicad_mod",+ "model_3d": "tps51463rger-hero.glb",+ "model_3d_plain": "tps51463rger.glb",+ "model_3d_step": "tps51463rger-etched.step",+ "model_3d_step_plain": "tps51463rger.step",+ "lbr": "tps51463rger.lbr"+ },+ "distributor_links": {+ "lcsc": "C2071867",+ "digikey": "296-40769-2-ND",+ "mouser": "595-TPS51463RGER"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:24:09Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-40769-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS51463RGER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground for the controller."+ },+ {+ "number": "2",+ "name": "VREF",+ "type": "power_out",+ "description": "2.0-V reference output; connect a 0.22-µF ceramic capacitor to GND."+ },+ {+ "number": "3",+ "name": "COMP",+ "type": "output",+ "description": "Connect a series R-C network between COMP and the VREF pin for loop compensation."+ },+ {+ "number": "4",+ "name": "SLEW",+ "type": "bidirectional",+ "description": "Programs startup and voltage-transition time via an external capacitor charged by a 10-µA current source."+ },+ {+ "number": "5",+ "name": "VOUT",+ "type": "input",+ "description": "Output voltage monitor input used for regulation, power-good, OVP and UVP sensing."+ },+ {+ "number": "6",+ "name": "MODE",+ "type": "input",+ "description": "Selects the switching frequency (700 kHz or 1 MHz) through the resistor connection on this pin, with a 1.8-V nominal threshold (see Table 3)."+ },+ {+ "number": "7",+ "name": "SW",+ "type": "bidirectional",+ "description": "Switching node output; connect to the external inductor."+ },+ {+ "number": "8",+ "name": "SW",+ "type": "bidirectional",+ "description": "Switching node output; connect to the external inductor."+ },+ {+ "number": "9",+ "name": "SW",+ "type": "bidirectional",+ "description": "Switching node output; connect to the external inductor."+ },+ {+ "number": "10",+ "name": "SW",+ "type": "bidirectional",+ "description": "Switching node output; connect to the external inductor."+ },+ {+ "number": "11",+ "name": "SW",+ "type": "bidirectional",+ "description": "Switching node output; connect to the external inductor."+ },+ {+ "number": "12",+ "name": "BST",+ "type": "input",+ "description": "Bootstrap supply for the internal high-side gate driver; connect a 0.1-µF bootstrap capacitor between this pin and SW."+ },+ {+ "number": "13",+ "name": "EN",+ "type": "input",+ "description": "Enable input for the SMPS; logic high is 0.8 V minimum and logic low is 0.3 V maximum."+ },+ {+ "number": "14",+ "name": "VID0",+ "type": "input",+ "description": "2-bit VID input (with VID1) selecting the output voltage per Table 1; logic high 0.8 V minimum, logic low 0.3 V maximum."+ },+ {+ "number": "15",+ "name": "VID1",+ "type": "input",+ "description": "2-bit VID input (with VID0) selecting the output voltage per Table 1; logic high 0.8 V minimum, logic low 0.3 V maximum."+ },+ {+ "number": "16",+ "name": "PGOOD",+ "type": "output",+ "description": "Open-drain power-good output; connect a pull-up resistor (100 kΩ recommended), with 0.3 V maximum pull-down voltage at 4 mA sink."+ },+ {+ "number": "17",+ "name": "V5FILT",+ "type": "power_in",+ "description": "5-V supply for analog circuits; 4.5 V to 5.5 V range, with UVLO at about 4.3 V."+ },+ {+ "number": "18",+ "name": "V5DRV",+ "type": "power_in",+ "description": "5-V supply for the internal gate driver; 4.5 V to 5.5 V range."+ },+ {+ "number": "19",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground; source terminal of the low-side power FET."+ },+ {+ "number": "20",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground; source terminal of the low-side power FET."+ },+ {+ "number": "21",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground; source terminal of the low-side power FET."+ },+ {+ "number": "22",+ "name": "VIN",+ "type": "power_in",+ "description": "Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V."+ },+ {+ "number": "23",+ "name": "VIN",+ "type": "power_in",+ "description": "Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V."+ },+ {+ "number": "24",+ "name": "VIN",+ "type": "power_in",+ "description": "Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V."+ },+ {+ "number": "25",+ "name": "Thermal Pad",+ "type": "power_in",+ "description": "Exposed thermal pad; connect directly to the system GND plane with multiple vias (must be soldered to the PCB)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin-function table on page 5 lists only pin 9 explicitly as SW; pins 7, 8, 10 and 11 are identif; The page 5 pin table groups these pins across wrapped rows; assignments were cross-checked against t; The datasheet pin table lists the exposed pad only as 'Thermal Pad' with no number; pad number 25 is"+ ],+ "pages_sent": 27,+ "cost_usd": 0.1143,+ "at": "2026-10-08T19:23:26"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/ds/symlink/tps51463.pdf",+ "pages": 27,+ "sha256": "31438a7865a64bbb",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps51463rger.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f7d256794c4147daf24dcae0554fae18510315e565ad1e239b475be7fef80d8b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps51463rger-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "12b326d14611aa114df8efc5f2c04f892522f0cde478e878b8c56f7c1229b3e9",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}