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TPS51463RGER

Public Made by Adom

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Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps51463rgerfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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PCB Footprint

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Datasheet

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Contents

README

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TPS51463RGER

Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)

TPS51463RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Signal ground for the controller.
2 VREF power_out 2.0-V reference output; connect a 0.22-µF ceramic capacitor to GND.
3 COMP output Connect a series R-C network between COMP and the VREF pin for loop compensation.
4 SLEW bidirectional Programs startup and voltage-transition time via an external capacitor charged by a 10-µA current source.
5 VOUT input Output voltage monitor input used for regulation, power-good, OVP and UVP sensing.
6 MODE input Selects the switching frequency (700 kHz or 1 MHz) through the resistor connection on this pin, with a 1.8-V nominal threshold (see Table 3).
7 SW bidirectional Switching node output; connect to the external inductor.
8 SW bidirectional Switching node output; connect to the external inductor.
9 SW bidirectional Switching node output; connect to the external inductor.
10 SW bidirectional Switching node output; connect to the external inductor.
11 SW bidirectional Switching node output; connect to the external inductor.
12 BST input Bootstrap supply for the internal high-side gate driver; connect a 0.1-µF bootstrap capacitor between this pin and SW.
13 EN input Enable input for the SMPS; logic high is 0.8 V minimum and logic low is 0.3 V maximum.
14 VID0 input 2-bit VID input (with VID1) selecting the output voltage per Table 1; logic high 0.8 V minimum, logic low 0.3 V maximum.
15 VID1 input 2-bit VID input (with VID0) selecting the output voltage per Table 1; logic high 0.8 V minimum, logic low 0.3 V maximum.
16 PGOOD output Open-drain power-good output; connect a pull-up resistor (100 kΩ recommended), with 0.3 V maximum pull-down voltage at 4 mA sink.
17 V5FILT power_in 5-V supply for analog circuits; 4.5 V to 5.5 V range, with UVLO at about 4.3 V.
18 V5DRV power_in 5-V supply for the internal gate driver; 4.5 V to 5.5 V range.
19 PGND power_in Power ground; source terminal of the low-side power FET.
20 PGND power_in Power ground; source terminal of the low-side power FET.
21 PGND power_in Power ground; source terminal of the low-side power FET.
22 VIN power_in Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V.
23 VIN power_in Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V.
24 VIN power_in Power supply input; drain terminal of the high-side power FET, recommended operating range -0.1 V to 6.5 V.
25 Thermal Pad power_in Exposed thermal pad; connect directly to the system GND plane with multiple vias (must be soldered to the PCB).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: TPS51463RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps51463rger-etched.step / tps51463rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps51463rger.step / tps51463rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 31438a7865a64bbb, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF