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Contents

README

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TPS51396ARJER

Texas Instruments · DC-DC Converters · QFN-20-EP(3x3)

TPS51396ARJER from Texas Instruments, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST power_in Supply input for gate drive voltage of high-side MOSFET; connect 0.1 μF bootstrap capacitor between BST and SW.
2 VIN power_in Input voltage supply pin for control circuitry rated 4.5V to 24V; connect input decoupling capacitors between VIN and GND.
3 VIN power_in Input voltage supply pin for control circuitry rated 4.5V to 24V; connect input decoupling capacitors between VIN and GND.
4 VIN power_in Input voltage supply pin for control circuitry rated 4.5V to 24V; connect input decoupling capacitors between VIN and GND.
5 VIN power_in Input voltage supply pin for control circuitry rated 4.5V to 24V; connect input decoupling capacitors between VIN and GND.
6 SW output Switch node terminal; connect output inductor to this pin.
7 GND power_in Power ground terminal for controller circuit and internal circuitry.
8 GND power_in Power ground terminal for controller circuit and internal circuitry.
9 PGOOD output Open drain power good indicator asserted low if output voltage out of threshold, overvoltage, thermal shutdown, EN shutdown, or soft start condition.
10 NC unconnected Not connected; can be connected to GND plane for improved thermal performance.
11 SS input Soft-start time selection pin; external capacitor sets timing with 1.3 ms default if not connected.
12 EN input Digital input enable pin to turn on/off buck converter with internal pull-down current when left open.
13 AGND power_in Analog ground; connect to GND plane with short trace.
14 FB input Converter feedback input connected to center tap of resistor divider between output voltage and AGND.
15 MODE input Light load operation mode selection pin; connect to resistor divider from VCC and AGND per table 7-1.
16 NC unconnected Not connected; can be connected to GND plane for improved thermal performance.
17 VCC power_in 5.0V internal LDO output supplying voltage to internal circuitry and gate driver; bypass with 1 μF capacitor.
18 GND power_in Power ground terminal for controller circuit and internal circuitry.
19 SW output Switch node terminal; connect output inductor to this pin.
20 SW output Switch node terminal; connect output inductor to this pin.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-20-EP(3x3)
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: TPS51396ARJER
  • Footprint: Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm
  • 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps51396arjer-etched.step / tps51396arjer-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps51396arjer.step / tps51396arjer.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 886c9ef21f4b86f1, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF