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TPS51275CRUKR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WQFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS51275CRUKR
Texas Instruments · DC-DC Converters · WQFN-20-EP(3x3)
TPS51275CRUKR from Texas Instruments, in a WQFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS1 | output | Sets the channel 1 overcurrent (OCL) trip level; CS1 sources about 10 µA and its voltage must stay between 0.2 V and 2 V over all operating temperatures. |
| 2 | VFB1 | input | Channel 1 voltage feedback input; OVP trips at 115% typ and UVP at 60% typ of the set output voltage. |
| 3 | VREG3 | power_out | 3.3-V LDO output that supplies the analog circuitry; add a ceramic capacitor of 1 µF or larger (X5R or better) close to the pin. |
| 4 | VFB2 | input | Channel 2 voltage feedback input; OVP trips at 115% typ and UVP at 60% typ of the set output voltage. |
| 5 | CS2 | output | Sets the channel 2 overcurrent (OCL) trip level; CS2 sources about 10 µA and its voltage must stay between 0.2 V and 2 V over all operating temperatures. |
| 6 | EN2 | input | Channel 2 enable input; the SMPS turns on above 1.6 V and off below 0.3 V. |
| 7 | PGOOD | output | Combined power-good open-drain output that must be pulled up to an external rail through a resistor; sink current is 6.5 mA max at 0.5 V. |
| 8 | SW2 | output | Channel 2 switch-node connection, which must be tied to the drain of the low-side MOSFET because the inductor current is sensed between GND and SW2. |
| 9 | VBST2 | input | Bootstrap supply input for the channel 2 high-side MOSFET driver; connect a capacitor from this pin to SW2. |
| 10 | DRVH2 | output | Channel 2 high-side gate driver output. |
| 11 | DRVL2 | output | Channel 2 low-side gate driver output. |
| 12 | VIN | power_in | Power conversion input, which must be supplied with the same voltage as the drain of the high-side MOSFETs of channels 1 and 2 (5 V to 24 V operating range). |
| 13 | VREG5 | power_out | 5-V LDO output that supplies the gate drivers (100 mA); add a ceramic capacitor of 1 µF or larger (X5R or better) close to the pin. |
| 14 | VO1 | input | Output voltage input for channel 1 that provides the 5-V switch-over input to VREG5 and VREG3. |
| 15 | DRVL1 | output | Channel 1 low-side gate driver output. |
| 16 | DRVH1 | output | Channel 1 high-side gate driver output. |
| 17 | VBST1 | input | Bootstrap supply input for the channel 1 high-side MOSFET driver; connect a capacitor from this pin to SW1. |
| 18 | SW1 | output | Channel 1 switch-node connection, which must be tied to the drain of the low-side MOSFET because the inductor current is sensed between GND and SW1. |
| 19 | VCLK | output | 260-kHz clock output for an external charge pump, available when EN1 is on and driven from VO1; leave open if unused. |
| 20 | EN1 | input | Channel 1 enable input; the SMPS turns on above 1.6 V and off below 0.3 V. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-20-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VFB regulation voltage (TA = 25°C) | VFBx | 1.99 | 2 | 2.01 | V | TA = 25°C | 5 |
| VFB regulation voltage (over operating free-air temperature range) | VFBx | 1.98 | 2 | 2.02 | V | 5 | |
| VREG5 output voltage | VVREG5 | 4.9 | 5 | 5.1 | V | TA = 25°C, No load, VVO1= 0 V | 5 |
| VREG5 output voltage | VVREG5 | 4.85 | 5 | 5.1 | V | VVIN > 7 V, VVO1= 0 V, IVREG5< 100 mA | 5 |
| VREG5 output voltage | VVREG5 | 4.5 | 4.75 | 5.1 | V | VVIN > 5 V, VVO1= 0 V, IVREG5< 20 mA | 5 |
| VREG3 output voltage | VVREG3 | 3.267 | 3.3 | 3.333 | V | No load, VVO1= 0 V, TA = 25°C | 5 |
| VREG3 output voltage | VVREG3 | 3.217 | 3.3 | 3.383 | V | VVIN > 7 V, VVO1= 0 V, IVREG3< 100 mA | 5 |
| VREG3 output voltage | VVREG3 | 3.234 | 3.3 | 3.366 | V | 5.5 V < VVIN, VVO1= 0 V, IVREG3< 35 mA | 5 |
| VREG3 output voltage | VVREG3 | 3.217 | 3.3 | 3.366 | V | VVIN > 5 V, VVO1= 0 V, IVREG3< 35 mA | 5 |
| CH1 frequency | fsw1 | 240 | 300 | 360 | kHz | TA = 25°C, VVIN= 20 V | 5 |
| CH2 frequency | fSW2 | 280 | 355 | 430 | kHz | TA = 25°C, VVIN= 20 V | 5 |
| Minimum off-time | tOFF(MIN) | 200 | 300 | 500 | ns | TA = 25°C | 5 |
| CS source current | ICS | 9 | 10 | 11 | µA | TA = 25°C, VCS= 0.4 V | 6 |
| CS current limit setting range | VCS | 0.2 | 2 | V | 6 | ||
| Zero cross detection offset | VZC | -1 | 1 | 3 | mV | TA = 25°C | 6 |
| EN input current | IEN | -1 | 1 | µA | VENx= 3.3 V | 6 | |
| OVP trip threshold | VOVP | 112.5 | 115 | 117.5 | % | 6 | |
| UVP trip threshold | VUVP | 55 | 60 | 65 | % | 6 | |
| PG threshold, lower (rising edge of PG-in) | VPGTH | 92.5 | 95 | 97.5 | % | Lower (rising edge of PG-in) | 6 |
| PG threshold, upper (rising edge of PG-out) | VPGTH | 107.5 | 110 | 112.5 | % | Upper (rising edge of PG-out) | 6 |
| VREG5 current limit | IVREG5 | 100 | 150 | mA | VVO1= 0 V, VVREG5= 4.5 V, VVIN= 7 V | 5 | |
| VREG3 current limit | IVREG3 | 100 | 150 | mA | VVO1= 0 V, VVREG3= 3.0 V, VVIN= 7 V | 5 | |
| Voltage on VBST1, VBST2 (absolute maximum) | -0.3 | 32 | V | 3 | |||
| Voltage on VBST1, VBST2 (note 3, with respect to SW terminals) | -0.3 | 6 | V | With respect to SW terminals (note 3) | 3 | ||
| Voltage on SW1, SW2 (absolute maximum) | -6 | 26 | V | 3 | |||
| Input voltage VIN (absolute maximum) | VIN | -0.3 | 26 | V | 3 | ||
| Input voltage EN1, EN2 (absolute maximum) | EN1, EN2 | -0.3 | 6 | V | 3 | ||
| Input voltage VFB1, VFB2 (absolute maximum) | VFB1, VFB2 | -0.3 | 3.6 | V | 3 | ||
| Input voltage VO1 (absolute maximum) | VO1 | -0.3 | 6 | V | 3 | ||
| Output voltage DRVH1, DRVH2 (absolute maximum) | DRVH1, DRVH2 | -6 | 32 | V | 3 | ||
| Output voltage DRVH1, DRVH2 (note 3, with respect to SW terminals) | DRVH1, DRVH2 | -0.3 | 6 | V | With respect to SW terminals (note 3) | 3 | |
| Output voltage DRVH1, DRVH2 (pulse width < 20 ns) | DRVH1, DRVH2 | -2.5 | 6 | V | Pulse width < 20 ns | 3 | |
| Output voltage DRVL1, DRVL2 (absolute maximum) | DRVL1, DRVL2 | -0.3 | 6 | V | 3 | ||
| Output voltage DRVL1, DRVL2 (pulse width < 20 ns) | DRVL1, DRVL2 | -2.5 | 6 | V | Pulse width < 20 ns | 3 | |
| Output voltage PGOOD, VCLK, VREG5 (absolute maximum) | PGOOD, VCLK, VREG5 | -0.3 | 6 | V | 3 | ||
| Voltage VREG3, CS1, CS2 (absolute maximum) | VREG3, CS1, CS2 | -0.3 | 3.6 | V | 3 | ||
| Junction temperature | TJ | 150 | °C | 3 | |||
| Storage temperature | TST | -55 | 150 | °C | 3 | ||
| Supply voltage VIN (recommended) | VIN | 5 | 24 | V | 4 | ||
| Input voltage VBST1, VBST2 (recommended) | VBST1, VBST2 | -0.1 | 30 | V | 4 | ||
| Input voltage VBST1, VBST2 (note 2, with respect to SW terminal) | VBST1, VBST2 | -0.1 | 5.5 | V | With respect to SW terminal (note 2) | 4 | |
| Input voltage SW1, SW2 (recommended) | SW1, SW2 | -5.5 | 24 | V | 4 | ||
| Input voltage EN1, EN2 (recommended) | EN1, EN2 | -0.1 | 5.5 | V | 4 | ||
| Input voltage VFB1, VFB2 (recommended) | VFB1, VFB2 | -0.1 | 3.5 | V | 4 | ||
| Input voltage VO1 (recommended) | VO1 | -0.1 | 5.5 | V | 4 | ||
| Output voltage DRVH1, DRVH2 (recommended) | DRVH1, DRVH2 | -5.5 | 30 | V | 4 | ||
| Output voltage DRVH1, DRVH2 (note 2, with respect to SW terminal) | DRVH1, DRVH2 | -0.1 | 5.5 | V | With respect to SW terminal (note 2) | 4 | |
| Output voltage DRVL1, DRVL2 (recommended) | DRVL1, DRVL2 | -0.1 | 5.5 | V | 4 | ||
| Output voltage PGOOD, VCLK, VREG5 (recommended) | PGOOD, VCLK, VREG5 | -0.1 | 5.5 | V | 4 | ||
| Output voltage VREG3, CS1, CS2 (recommended) | VREG3, CS1, CS2 | -0.1 | 3.5 | V | 4 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| Junction-to-ambient thermal resistance | θJA | 94.1 | °C/W | 3 | |||
| Junction-to-case (top) thermal resistance | θJCtop | 58.1 | °C/W | 3 | |||
| Junction-to-board thermal resistance | θJB | 64.3 | °C/W | 3 | |||
| Junction-to-top characterization parameter | ψJT | 31.8 | °C/W | 3 | |||
| Junction-to-board characterization parameter | ψJB | 58 | °C/W | 3 | |||
| Junction-to-case (bottom) thermal resistance | θJCbot | 5.9 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
TPS51275CRUKR - Footprint:
Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm - 3D model: WQFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps51275crukr-etched.step/tps51275crukr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps51275crukr.step/tps51275crukr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
3995a003a7a617e9, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).