component
TPS51221RTVR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 22d ago |
| viewers | 22d ago |
| package.json | 22d ago |
| page.json | 16d ago |
| README.md | 16d ago |
| tps51221rtvr-etched.glb | 22d ago |
| tps51221rtvr-etched.step | 22d ago |
| tps51221rtvr-hero.glb | 22d ago |
| tps51221rtvr-hero.overlay.json | 22d ago |
| tps51221rtvr.glb | 22d ago |
| tps51221rtvr.kicad_mod | 22d ago |
| tps51221rtvr.kicad_sym | 22d ago |
| tps51221rtvr.lbr | 22d ago |
| tps51221rtvr.step | 22d ago |
TPS51221RTVR
Texas Instruments · DC-DC Converters · WQFN-32-EP(5x5)
TPS51221RTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRVH1 | output | Channel 1 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node referenced floating driver whose drive voltage equals the VBST-to-SW voltage. |
| 2 | V5SW | power_in | VREG5 switchover supply input; when EN1 is high, PGOOD1 indicates good and V5SW is above 4.8 V, VREG5 switches over to V5SW, with an absolute maximum range of -1 V to 7 V. |
| 3 | RF | bidirectional | Frequency-setting pin, where a resistor to signal GND sets the switching frequency and an external clock can be connected for synchronization; absolute maximum range is -0.3 V to 7 V. |
| 4 | EN1 | input | Channel 1 SMPS enable pin, where greater than 0.55 V and less than 6 V turns it on or it may be left floating, connect to GND to disable it, and the soft-start capacitor attaches here. |
| 5 | PGOOD1 | output | Channel 1 power-good window comparator output, where the applied voltage must be less than 6 V and a pull-up resistor of 100 kΩ to 1 MΩ is recommended. |
| 6 | SKIPSEL1 | input | Channel 1 skip-mode selection pin, where GND selects continuous conduction, VREF2 selects auto skip, VREG3 selects OOA auto skip with maximum 7 skips (use below 400 kHz), and VREG5 selects OOA auto skip with maximum 15 skips (use above 400 kHz). |
| 7 | CSP1 | bidirectional | Channel 1 current-sense comparator positive input, where an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop and 0.1 µF is a good starting value. |
| 8 | CSN1 | input | Channel 1 current-sense comparator negative input, which also powers the current-sense circuit for output voltages of 5 V or higher and is used for output discharge. |
| 9 | VFB1 | input | Channel 1 SMPS feedback input, to which the feedback resistor divider connects, referenced to signal GND, with absolute maximum range -0.3 V to 7 V. |
| 10 | COMP1 | input | Channel 1 loop compensation pin (error amplifier output), where R and optionally C connect from this pin to VREF2 for current-mode loop compensation. |
| 11 | IMON1 | output | Channel 1 current monitor output, where an RC filter is recommended. |
| 12 | EN | input | Enable pin for the VREF2 and VREG5 linear regulators, where greater than 1.2 V and less than 6 V turns them on and connecting to GND disables them. |
| 13 | VREF2 | output | 2-V reference output, which must be bypassed to signal GND with a 0.22 µF ceramic capacitor. |
| 14 | TRIP | input | Over-current trip level and discharge mode selection pin, where GND selects VOCL-ULV with discharge on, VREF2 selects VOCL-ULV with discharge off, VREG3 selects VOCL-LV with discharge off, and VREG5 selects VOCL-LV with discharge on. |
| 15 | COMP2 | input | Channel 2 loop compensation pin (error amplifier output), where R and optionally C connect from this pin to VREF2 for current-mode loop compensation. |
| 16 | VFB2 | input | Channel 2 SMPS feedback input, to which the feedback resistor divider connects, referenced to signal GND, with absolute maximum range -0.3 V to 7 V. |
| 17 | CSN2 | input | Channel 2 current-sense comparator negative input, which also powers the current-sense circuit for output voltages of 5 V or higher and is used for output discharge. |
| 18 | CSP2 | bidirectional | Channel 2 current-sense comparator positive input, where an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop and 0.1 µF is a good starting value. |
| 19 | SKIPSEL2 | input | Channel 2 skip-mode selection pin, where GND selects continuous conduction, VREF2 selects auto skip, VREG3 selects OOA auto skip with maximum 7 skips (use below 400 kHz), and VREG5 selects OOA auto skip with maximum 15 skips (use above 400 kHz). |
| 20 | PGOOD2 | output | Channel 2 power-good window comparator output, where the applied voltage must be less than 6 V and a pull-up resistor of 100 kΩ to 1 MΩ is recommended. |
| 21 | EN2 | input | Channel 2 SMPS enable pin, where greater than 0.55 V and less than 6 V turns it on or it may be left floating, connect to GND to disable it, and the soft-start capacitor attaches here. |
| 22 | VREG3 | power_out | Always-alive 3.3 V, 10 mA low-dropout linear regulator output, which runs from VIN or from VREG5 when switched over and must be bypassed to signal GND with more than 1 µF ceramic. |
| 23 | VIN | power_in | Supply input for the 5 V and 3.3 V linear regulators, typically connected to VBAT, with absolute maximum range -0.3 V to 30 V. |
| 24 | DRVH2 | output | Channel 2 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node referenced floating driver whose drive voltage equals the VBST-to-SW voltage. |
| 25 | SW2 | bidirectional | Channel 2 high-side MOSFET gate driver return, referenced to the switching node. |
| 26 | VBST2 | input | Boot-strap supply input for the channel 2 high-side driver, requiring a capacitor of 0.1 µF or greater from this pin to SW2, with an optional Schottky diode from VREG5 permitted. |
| 27 | DRVL2 | output | Channel 2 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver. |
| 28 | GND | power_in | Ground. |
| 29 | VREG5 | power_out | 5-V, 100-mA low-dropout linear regulator output, bypassed to power GND with a 10 µF ceramic capacitor, running from VIN and switching over to V5SW when 4.8 V or above is provided. |
| 30 | DRVL1 | output | Channel 1 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver. |
| 31 | VBST1 | input | Boot-strap supply input for the channel 1 high-side driver, requiring a capacitor of 0.1 µF or greater from this pin to SW1, with an optional Schottky diode from VREG5 permitted. |
| 32 | SW1 | bidirectional | Channel 1 high-side MOSFET gate driver return, referenced to the switching node. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VIN | 4.5 | 28 | V | 4 | ||
| Supply voltage V5SW I/O | V5SW | -0.8 | 6 | V | 4 | ||
| VBST1, VBST2 I/O voltage | VBST1, VBST2 | -0.1 | 33 | V | 4 | ||
| DRVH1, DRVH2 I/O voltage | DRVH1, DRVH2 | -4 | 33 | V | 4 | ||
| DRVH1, DRVH2 voltage with respect to SW1, SW2 | DRVH1, DRVH2 (wrt SW1, 2) | -0.1 | 6 | V | 4 | ||
| SW1, SW2 I/O voltage | SW1, SW2 | -4 | 28 | V | 4 | ||
| CSP1, CSP2, CSN1, CSN2 I/O voltage | CSP1, CSP2, CSN1, CSN2 | -0.8 | 13 | V | 4 | ||
| EN, EN1, EN2, VFB1, VFB2, TRIP, DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2, PGOOD1, PGOOD2, SKIPSEL1, SKIPSEL2, IMON1 I/O voltage | -0.1 | 6 | V | 4 | |||
| VREG3 I/O voltage | VREG3 | -0.1 | 3.5 | V | 4 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| VIN voltage range | VIN | -0.3 | 30 | V | 3 | ||
| VBST1, VBST2 voltage range | VBST1, VBST2 | -0.3 | 35 | V | 3 | ||
| VBST1, VBST2 voltage with respect to SW | VBST1, VBST2 | -0.3 | 7 | V | 3 | ||
| SW1, SW2 voltage range | SW1, SW2 | -5 | 30 | V | 3 | ||
| CSP1, CSP2, CSN1, CSN2 voltage range | CSP1, CSP2, CSN1, CSN2 | -1 | 13.5 | V | 3 | ||
| EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2 voltage range | EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2 | -0.3 | 7 | V | 3 | ||
| V5SW voltage range | V5SW | -1 | 7 | V | 3 | ||
| V5SW voltage to VREG5 | V5SW (to VREG5) | -7 | 7 | V | 3 | ||
| DRVH1, DRVH2 voltage range | DRVH1, DRVH2 | -5 | 35 | V | 3 | ||
| DRVH1, DRVH2 voltage with respect to SW | DRVH1, DRVH2 | -0.3 | 7 | V | 3 | ||
| DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2, IMON1, PGOOD1, PGOOD2 voltage range | DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2, IMON1, PGOOD1, PGOOD2 | -0.3 | 7 | V | 3 | ||
| VREG3 voltage range | VREG3 | -0.3 | 3.6 | V | 3 | ||
| Operating junction temperature range | TJ | -40 | 125 | °C | 3 | ||
| Storage temperature | Tst | -55 | 150 | °C | 3 | ||
| Power rating, 32-pin RTV package | 1.7 | W | TA < 25°C; 2 oz trace and copper pad with solder | 3 | |||
| Derating factor above TA = 25°C, 32-pin RTV package | 17 | mW/°C | Above TA = 25°C; 2 oz trace and copper pad with solder | 3 | |||
| Power rating at TA = 85°C, 32-pin RTV package | 0.7 | W | TA = 85°C; 2 oz trace and copper pad with solder | 3 | |||
| VIN shutdown current | IVINSDN | 7 | 15 | µA | TA = 25°C, No Load, EN = 0V, V5SW = 0 V | 5 | |
| VIN standby current | IVINSTBY1 | 80 | 120 | µA | TA = 25°C, No Load, EN1=EN2=V5SW = 0 V | 5 | |
| VREF2 output voltage | VVREF2 | 1.98 | 2 | 2.02 | V | IVREF2 < ±10 µA, TA = 25°C | 5 |
| VREF2 output voltage (wide range) | VVREF2 | 1.97 | 2 | 2.03 | V | IVREF2 < ±100 µA, 4.5V < VIN < 25 V | 5 |
| VREG3 output voltage | VVREG3 | 3.135 | 3.3 | 3.4 | V | V5SW = 0 V, 0 mA < IVREG3 < 10 mA, 5.5 V < VIN < 25 V | 5 |
| VREG3 output current | IVREG3 | 10 | 15 | 20 | mA | VREG3 = 3 V | 5 |
| VREG5 output voltage | VVREG5 | 4.9 | 5.03 | 5.15 | V | V5SW = 0 V, 0 mA < IVREG5 < 100 mA, 6 V < VIN < 25 V | 5 |
| VREG5 output voltage (5.5 V input) | VVREG5 | 4.5 | 5.03 | 5.15 | V | V5SW = 0 V, 0 mA < IVREG5 < 100 mA, 5.5 V < VIN < 25 V | 5 |
| VREG5 output current | IVREG5 | 100 | 150 | 200 | mA | V5SW = 0 V, VREG5 = 4.5 V | 5 |
| VREG5 output current with V5SW | IVREG5 | 200 | 300 | 400 | mA | V5SW = 5 V, VREG5 = 4.5 V | 5 |
| Switchover threshold (turning on) | VTHV5SW | 4.55 | 4.7 | 4.8 | V | Turning on | 5 |
| VFB regulation voltage | VVFB | 0.9925 | 1 | 1.0075 | V | TA = 25°C, No Load | 5 |
| VFB regulation voltage tolerance over temperature | VVFB | 0.99 | 1 | 1.01 | V | TA = –40°C to 85°C, No Load | 5 |
| VFB input current | IVFB | -50 | 50 | nA | VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C | 5 | |
| CSNx discharge resistance | RDischg | 20 | 40 | Ω | ENx = 0 V, CSNx = 0.5 V, TA = 25°C | 5 | |
| PG threshold, PG in from lower | VTHPG | 92.5 | 95 | 97.5 | % | PG in from lower | 6 |
| PG threshold, PG in from higher | VTHPG | 102.5 | 105 | 107.5 | % | PG in from higher | 6 |
| Switching frequency | fSW | 273 | 303 | 333 | kHz | Rf = 330 kΩ | 6 |
| RF threshold, low to high | VTHRF | 0.7 | 1.3 | 2 | V | Lo to Hi | 6 |
| Minimum on-time | tONMIN | 120 | 150 | ns | VDRVH = 90% to 10%, No Load | 6 | |
| Current limit threshold (ultra low voltage), TA = 25°C | VOCL-ULV | 27 | 31 | 35 | mV | TRIP = 0V/2V, TA = 25°C | 6 |
| Current limit threshold (low voltage), TA = 25°C | VOCL-LV | 56 | 60 | 64 | mV | TRIP = 3.3V/5V, TA = 25°C | 6 |
| Negative current limit threshold (ULV), TA = 25°C | VOCLN-ULV | -24 | -31 | -38 | mV | TRIP = 0V/2V, TA = 25°C | 6 |
| OVP trip threshold | VOVP | 110 | 115 | 120 | % | OVP detect | 7 |
| UVP trip threshold | VUVP | 65 | 70 | 73 | % | UVP detect | 7 |
| VREF2 UVLO threshold, wake up | VUVREF2 | 1.7 | 1.8 | 1.9 | V | Wake up | 7 |
| VREG5 UVLO threshold, wake up | VUVREG5 | 4.1 | 4.2 | 4.3 | V | Wake up | 7 |
| EN threshold, wake up | VEN | 0.8 | 1 | 1.2 | V | Wake up | 7 |
| EN1/EN2 threshold, wake up | VEN12 | 0.45 | 0.5 | 0.55 | V | Wake up | 7 |
| EN1/EN2 source current | IEN12 | 1.5 | 2 | 2.6 | µA | VEN1/EN2 = 0V | 7 |
| Current monitor output voltage | VIMON | 2.65 | 2.95 | 3.25 | V | TRIP = 0V/2V, VCSPx-CSNx = 30 mV, 0.95V<CNSx<12.6V, TA = 25°C | 8 |
| Boot strap forward voltage | VFBST | 0.1 | 0.2 | V | VVREG5-VBST, IF = 10 mA, TA = 25°C | 7 |
CAD (KiCad official)
- Symbol:
TPS51221RTVR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps51221rtvr-etched.step/tps51221rtvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps51221rtvr.step/tps51221rtvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
d3ac05277fe67fc8, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).