component
TPS51220ARTVR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownTPS51220ARTVR
Texas Instruments · DC-DC Converters · WQFN-32-EP(5x5)
TPS51220ARTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRVH1 | output | High-side MOSFET gate driver output for channel 1; source 1.7 Ω, sink 1.0 Ω, SW1-node referenced floating driver, drive voltage corresponds to VBST1 to SW1 voltage. |
| 2 | V5SW | power_in | VREG5 switchover power supply input; when EN1 is high, PGOOD1 is good and V5SW > 4.8 V, the internal 5-V LDO is shut off and VREG5 is switched to V5SW. |
| 3 | RF | bidirectional | Frequency setting pin; connect a resistor to signal GND to set switching frequency, or connect to an external clock for synchronization. |
| 4 | EN1 | input | Channel 1 SMPS enable pin; apply greater than 0.55 V and less than 6 V to turn on, or leave floating; connect to GND to disable; adjustable soft-start capacitance may be attached here. |
| 5 | PGOOD1 | output | Powergood window comparator output for channel 1; recommended applied voltage less than 6 V, recommended pull-up resistance 100 kΩ to 1 MΩ. |
| 6 | SKIPSEL1 | input | Skip mode selection pin for channel 1; GND=continuous conduction, VREF2=Auto Skip, VREG3=OOA Auto Skip max 7 skips, VREG5=OOA Auto Skip max 15 skips. |
| 7 | CSP1 | bidirectional | Current sense comparator (+) input for channel 1; use an RC network with X5R/X7R ceramic capacitor (0.1 µF typical) to extract voltage drop across DCR. |
| 8 | CSN1 | input | Current sense comparator (-) input for channel 1; used as power supply for the channel-1 current sense circuit at 5 V or higher output settings, and as the output discharge terminal. |
| 9 | VFB1 | input | SMPS voltage feedback input for channel 1; connect the feedback resistor divider, referenced to signal GND. |
| 10 | COMP1 | input | Loop compensation pin for channel 1 current-mode error amplifier output; connect R (and C if required) from this pin to VREF2 for loop compensation. |
| 11 | FUNC | input | Control architecture and OVP selection pin: GND=Current mode/OVP enable, VREF2=D-CAP mode/OVP disable, VREG3=D-CAP mode/OVP enable, VREG5=Current mode/OVP disable. |
| 12 | EN | input | VREF2 and VREG5 linear regulator enable pin; apply greater than 1.2 V and less than 6 V to turn on; connect to GND to disable. |
| 13 | VREF2 | power_out | 2-V reference output; bypass to signal GND with 0.22-µF ceramic capacitance. |
| 14 | TRIP | input | Overcurrent trip level and discharge mode selection pin: GND=V(OCL-ULV) discharge on, VREF2=V(OCL-ULV) discharge off, VREG3=V(OCL-LV) discharge off, VREG5=V(OCL-LV) discharge on. |
| 15 | COMP2 | input | Ramp compensation/loop compensation pin for channel 2; connect R (10 kΩ typical, 6 kΩ-20 kΩ range) from this pin to VREF2 for D-CAP mode ramp compensation or current-mode loop compensation. |
| 16 | VFB2 | input | SMPS voltage feedback input for channel 2; connect the feedback resistor divider, referenced to signal GND. |
| 17 | CSN2 | input | Current sense comparator (-) input for channel 2; used as power supply for the channel-2 current sense circuit at 5 V or higher output settings, and as the output discharge terminal. |
| 18 | CSP2 | bidirectional | Current sense comparator (+) input for channel 2; use an RC network with X5R/X7R ceramic capacitor (0.1 µF typical) to extract voltage drop across DCR. |
| 19 | SKIPSEL2 | input | Skip mode selection pin for channel 2; GND=continuous conduction, VREF2=Auto Skip, VREG3=OOA Auto Skip max 7 skips, VREG5=OOA Auto Skip max 15 skips. |
| 20 | PGOOD2 | output | Powergood window comparator output for channel 2; recommended applied voltage less than 6 V, recommended pull-up resistance 100 kΩ to 1 MΩ. |
| 21 | EN2 | input | Channel 2 SMPS enable pin; apply greater than 0.55 V and less than 6 V to turn on, or leave floating; connect to GND to disable; adjustable soft-start capacitance may be attached here. |
| 22 | VREG3 | power_out | Always-alive 3.3-V, 10-mA LDO output; bypass to signal GND with more than 1-µF ceramic capacitance; runs from VIN or from VREG5 when switched over to V5SW. |
| 23 | VIN | power_in | Supply input for the 5-V and 3.3-V linear regulators; typically connected to VBAT. |
| 24 | DRVH2 | output | High-side MOSFET gate driver output for channel 2; source 1.7 Ω, sink 1.0 Ω, SW2-node referenced floating driver, drive voltage corresponds to VBST2 to SW2 voltage. |
| 25 | SW2 | bidirectional | High-side MOSFET gate driver return for channel 2 (switch node). |
| 26 | VBST2 | power_in | Supply input for channel-2 high-side N-channel FET driver (boot strap terminal); connect a capacitor (0.1 µF or greater recommended) from this pin to SW2; an optional Schottky diode from VREG5 is allowed. |
| 27 | DRVL2 | output | Low-side MOSFET gate driver output for channel 2; source 1.3 Ω, sink 0.7 Ω, GND-referenced driver. |
| 28 | GND | power_in | Signal ground reference for the device. |
| 29 | VREG5 | power_out | 5-V, 100-mA LDO output; bypass to power GND with a 10-µF (min 4.7-µF) ceramic capacitor; runs from VIN, internally connected to VBST and DRVL, shuts off with EN, switches over to V5SW when 4.8 V or above is provided. |
| 30 | DRVL1 | output | Low-side MOSFET gate driver output for channel 1; source 1.3 Ω, sink 0.7 Ω, GND-referenced driver. |
| 31 | VBST1 | power_in | Supply input for channel-1 high-side N-channel FET driver (boot strap terminal); connect a capacitor (0.1 µF or greater recommended) from this pin to SW1; an optional Schottky diode from VREG5 is allowed. |
| 32 | SW1 | bidirectional | High-side MOSFET gate driver return for channel 1 (switch node). |
| 33 | PowerPAD | power_in | Exposed thermal pad (PowerPAD); must be soldered to the PCB and connected to the internal GND plane through five or more 0.33-mm vias for thermal dissipation; do not connect the GND pin to this pad on the surface layer. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
TPS51220ARTVR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps51220artvr-etched.step/tps51220artvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps51220artvr.step/tps51220artvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (55 pp, sha256
6e980b37451f3708, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).