component

TPS51220ARSNT

Public Made by Adom

by adom

Texas Instruments Power Management - Specialized, QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps51220arsntfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 20d ago
viewers tps51220arsnt: viewers · Ray 20d ago
package.json Publish 0.1.0 · Ray 20d ago
page.json Set visibility: public · Ray 20d ago
README.md Initial commit: component/tps51220arsnt · Ray 20d ago
tps51220arsnt-etched.glb tps51220arsnt: factory component page (tier=lcsc) · Ray 20d ago
tps51220arsnt-etched.step tps51220arsnt: factory component page (tier=lcsc) · Ray 20d ago
tps51220arsnt-hero.glb tps51220arsnt: hero GLB from the etched model (keeps the MPN mark) · Ray 20d ago
tps51220arsnt-hero.overlay.json Publish 0.1.0 · Ray 20d ago
tps51220arsnt.glb Publish 0.1.0 · Ray 20d ago
tps51220arsnt.kicad_mod Publish 0.1.0 · Ray 20d ago
tps51220arsnt.kicad_sym Publish 0.1.0 · Ray 20d ago
tps51220arsnt.lbr Publish 0.1.0 · Ray 20d ago
tps51220arsnt.step Publish 0.1.0 · Ray 20d ago

TPS51220ARSNT

Texas Instruments · Power Management - Specialized · QFN-32-EP(4x4)

TPS51220ARSNT from Texas Instruments, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRVH1 output Channel 1 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node-referenced floating driver with drive voltage equal to VBST-to-SW.
2 V5SW input 5-V switchover supply input; when EN1 is high, PGOOD1 indicates good and V5SW is above 4.8 V, VREG5 switches over to V5SW.
3 RF bidirectional Frequency setting pin: connect a frequency-setting resistor to GND, or an external clock for synchronization; the fixed frequency is adjustable from 200 kHz to 1 MHz.
4 EN1 input Channel 1 SMPS enable; apply greater than 0.55 V and less than 6 V to turn on or leave floating, connect to GND to disable, and the adjustable soft-start capacitor attaches here.
5 PGOOD1 output Channel 1 powergood window comparator output; recommended applied voltage less than 6 V and recommended pull-up resistor 100 kΩ to 1 MΩ.
6 SKIPSEL1 input Channel 1 skip mode selection: GND selects continuous conduction, VREF2 auto skip, VREG3 OOA auto skip (max 7 skips, suitable for fsw < 400 kHz), VREG5 OOA auto skip (max 15 skips, suitable for fsw ≥ 400 kHz).
7 CSP1 bidirectional Channel 1 current sense comparator positive input; an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop, 0.1 µF suggested as a starting value.
8 CSN1 input Channel 1 current sense comparator negative input, also the supply for the current sense circuit at 5 V or higher output settings and the output discharge terminal.
9 VFB1 input Channel 1 SMPS voltage feedback input, connected to the feedback resistor divider and referred to signal GND; regulation voltage 1.000 V nominal.
10 COMP1 input Channel 1 loop compensation pin for current mode (error amplifier output), connect R (and C if required) to VREF2; in D-CAP mode, R to VREF2 sets ramp compensation, 10 kΩ suggested (6 kΩ to 20 kΩ).
11 FUNC input Control architecture and OVP selection: GND for current mode with OVP enabled, VREF2 for D-CAP mode with OVP disabled, VREG3 for D-CAP mode with OVP enabled, VREG5 for current mode with OVP disabled.
12 EN input VREF2 and VREG5 linear regulator enable; apply greater than 1.2 V and less than 6 V to turn on, connect to GND to disable.
13 VREF2 output 2-V reference output, to be bypassed to signal GND with 0.22 µF of ceramic capacitance.
14 TRIP input Overcurrent trip level and discharge mode selection: GND gives V(OCL-ULV) with discharge on, VREF2 gives V(OCL-ULV) with discharge off, VREG3 gives V(OCL-LV) with discharge off, VREG5 gives V(OCL-LV) with discharge on.
15 COMP2 input Channel 2 loop compensation pin for current mode (error amplifier output), connect R (and C if required) to VREF2; in D-CAP mode, R to VREF2 sets ramp compensation, 10 kΩ suggested (6 kΩ to 20 kΩ).
16 VFB2 input Channel 2 SMPS voltage feedback input, connected to the feedback resistor divider and referred to signal GND.
17 CSN2 input Channel 2 current sense comparator negative input, also the supply for the current sense circuit at 5 V or higher output settings and the output discharge terminal.
18 CSP2 bidirectional Channel 2 current sense comparator positive input; an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop, 0.1 µF suggested as a starting value.
19 SKIPSEL2 input Channel 2 skip mode selection: GND selects continuous conduction, VREF2 auto skip, VREG3 OOA auto skip (max 7 skips, suitable for fsw < 400 kHz), VREG5 OOA auto skip (max 15 skips, suitable for fsw ≥ 400 kHz).
20 PGOOD2 output Channel 2 powergood window comparator output; recommended applied voltage less than 6 V and recommended pull-up resistor 100 kΩ to 1 MΩ.
21 EN2 input Channel 2 SMPS enable; apply greater than 0.55 V and less than 6 V to turn on or leave floating, connect to GND to disable, and the adjustable soft-start capacitor attaches here.
22 VREG3 output Always-alive 3.3-V, 10-mA low-dropout linear regulator output, bypass to signal GND with more than 1 µF ceramic; runs from VIN or from VREG5 when switched over to V5SW.
23 VIN power_in Supply input for the 5-V and 3.3-V linear regulators, typically connected to VBAT; input range 4.5 V to 32 V.
24 DRVH2 output Channel 2 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node-referenced floating driver with drive voltage equal to VBST-to-SW.
25 SW2 bidirectional Channel 2 high-side MOSFET gate driver return (switch node), referenced for the floating high-side driver.
26 VBST2 input Channel 2 bootstrap supply input for the high-side N-channel FET driver; connect a capacitor of 0.1 µF or greater from this pin to SW2, an additional Schottky diode from VREG5 is optional.
27 DRVL2 output Channel 2 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver.
28 GND power_in Ground.
29 VREG5 output 5-V, 100-mA low-dropout linear regulator output, bypass to power GND with 10 µF ceramic; runs from VIN and switches over to V5SW when 4.8 V or above is provided.
30 DRVL1 output Channel 1 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver.
31 VBST1 input Channel 1 bootstrap supply input for the high-side N-channel FET driver; connect a capacitor of 0.1 µF or greater from this pin to SW1, an additional Schottky diode from VREG5 is optional.
32 SW1 bidirectional Channel 1 high-side MOSFET gate driver return (switch node), referenced for the floating high-side driver.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-32-EP(4x4)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS51220ARSNT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps51220arsnt-etched.step / tps51220arsnt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps51220arsnt.step / tps51220arsnt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 6e980b37451f3708, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF