component
TPS51220ARSNT
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+69@@ -0,0 +1,69 @@+# TPS51220ARSNT++**Texas Instruments** · Power Management - Specialized · QFN-32-EP(4x4)++TPS51220ARSNT from Texas Instruments, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DRVH1 | output | Channel 1 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node-referenced floating driver with drive voltage equal to VBST-to-SW. |+| 2 | V5SW | input | 5-V switchover supply input; when EN1 is high, PGOOD1 indicates good and V5SW is above 4.8 V, VREG5 switches over to V5SW. |+| 3 | RF | bidirectional | Frequency setting pin: connect a frequency-setting resistor to GND, or an external clock for synchronization; the fixed frequency is adjustable from 200 kHz to 1 MHz. |+| 4 | EN1 | input | Channel 1 SMPS enable; apply greater than 0.55 V and less than 6 V to turn on or leave floating, connect to GND to disable, and the adjustable soft-start capacitor attaches here. |+| 5 | PGOOD1 | output | Channel 1 powergood window comparator output; recommended applied voltage less than 6 V and recommended pull-up resistor 100 kΩ to 1 MΩ. |+| 6 | SKIPSEL1 | input | Channel 1 skip mode selection: GND selects continuous conduction, VREF2 auto skip, VREG3 OOA auto skip (max 7 skips, suitable for fsw < 400 kHz), VREG5 OOA auto skip (max 15 skips, suitable for fsw ≥ 400 kHz). |+| 7 | CSP1 | bidirectional | Channel 1 current sense comparator positive input; an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop, 0.1 µF suggested as a starting value. |+| 8 | CSN1 | input | Channel 1 current sense comparator negative input, also the supply for the current sense circuit at 5 V or higher output settings and the output discharge terminal. |+| 9 | VFB1 | input | Channel 1 SMPS voltage feedback input, connected to the feedback resistor divider and referred to signal GND; regulation voltage 1.000 V nominal. |+| 10 | COMP1 | input | Channel 1 loop compensation pin for current mode (error amplifier output), connect R (and C if required) to VREF2; in D-CAP mode, R to VREF2 sets ramp compensation, 10 kΩ suggested (6 kΩ to 20 kΩ). |+| 11 | FUNC | input | Control architecture and OVP selection: GND for current mode with OVP enabled, VREF2 for D-CAP mode with OVP disabled, VREG3 for D-CAP mode with OVP enabled, VREG5 for current mode with OVP disabled. |+| 12 | EN | input | VREF2 and VREG5 linear regulator enable; apply greater than 1.2 V and less than 6 V to turn on, connect to GND to disable. |+| 13 | VREF2 | output | 2-V reference output, to be bypassed to signal GND with 0.22 µF of ceramic capacitance. |+| 14 | TRIP | input | Overcurrent trip level and discharge mode selection: GND gives V(OCL-ULV) with discharge on, VREF2 gives V(OCL-ULV) with discharge off, VREG3 gives V(OCL-LV) with discharge off, VREG5 gives V(OCL-LV) with discharge on. |+| 15 | COMP2 | input | Channel 2 loop compensation pin for current mode (error amplifier output), connect R (and C if required) to VREF2; in D-CAP mode, R to VREF2 sets ramp compensation, 10 kΩ suggested (6 kΩ to 20 kΩ). |+| 16 | VFB2 | input | Channel 2 SMPS voltage feedback input, connected to the feedback resistor divider and referred to signal GND. |+| 17 | CSN2 | input | Channel 2 current sense comparator negative input, also the supply for the current sense circuit at 5 V or higher output settings and the output discharge terminal. |+| 18 | CSP2 | bidirectional | Channel 2 current sense comparator positive input; an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop, 0.1 µF suggested as a starting value. |+| 19 | SKIPSEL2 | input | Channel 2 skip mode selection: GND selects continuous conduction, VREF2 auto skip, VREG3 OOA auto skip (max 7 skips, suitable for fsw < 400 kHz), VREG5 OOA auto skip (max 15 skips, suitable for fsw ≥ 400 kHz). |+| 20 | PGOOD2 | output | Channel 2 powergood window comparator output; recommended applied voltage less than 6 V and recommended pull-up resistor 100 kΩ to 1 MΩ. |+| 21 | EN2 | input | Channel 2 SMPS enable; apply greater than 0.55 V and less than 6 V to turn on or leave floating, connect to GND to disable, and the adjustable soft-start capacitor attaches here. |+| 22 | VREG3 | output | Always-alive 3.3-V, 10-mA low-dropout linear regulator output, bypass to signal GND with more than 1 µF ceramic; runs from VIN or from VREG5 when switched over to V5SW. |+| 23 | VIN | power_in | Supply input for the 5-V and 3.3-V linear regulators, typically connected to VBAT; input range 4.5 V to 32 V. |+| 24 | DRVH2 | output | Channel 2 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node-referenced floating driver with drive voltage equal to VBST-to-SW. |+| 25 | SW2 | bidirectional | Channel 2 high-side MOSFET gate driver return (switch node), referenced for the floating high-side driver. |+| 26 | VBST2 | input | Channel 2 bootstrap supply input for the high-side N-channel FET driver; connect a capacitor of 0.1 µF or greater from this pin to SW2, an additional Schottky diode from VREG5 is optional. |+| 27 | DRVL2 | output | Channel 2 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver. |+| 28 | GND | power_in | Ground. |+| 29 | VREG5 | output | 5-V, 100-mA low-dropout linear regulator output, bypass to power GND with 10 µF ceramic; runs from VIN and switches over to V5SW when 4.8 V or above is provided. |+| 30 | DRVL1 | output | Channel 1 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver. |+| 31 | VBST1 | input | Channel 1 bootstrap supply input for the high-side N-channel FET driver; connect a capacitor of 0.1 µF or greater from this pin to SW1, an additional Schottky diode from VREG5 is optional. |+| 32 | SW1 | bidirectional | Channel 1 high-side MOSFET gate driver return (switch node), referenced for the floating high-side driver. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFN-32-EP(4x4) |+| Category | Power Management (PMIC) |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `TPS51220ARSNT`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm`+- 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `tps51220arsnt-etched.step` / `tps51220arsnt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps51220arsnt.step` / `tps51220arsnt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps51220a) (55 pp, sha256 `6e980b37451f3708`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps51220arsnt-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps51220arsnt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps51220arsnt.kicad_sym",+ "tps51220arsnt.kicad_mod",+ "tps51220arsnt.glb",+ "tps51220arsnt.step",+ "tps51220arsnt.lbr",+ "docs/hero.png",+ "docs/tps51220arsnt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps51220arsnt-hero.glb",+ "tps51220arsnt-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS51220ARSNT",+ "manufacturer": "Texas Instruments",+ "package": "QFN-32-EP(4x4)",+ "pin_count": 33,+ "category": "Power Management (PMIC)",+ "subcategory": "Power Management - Specialized",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps51220a",+ "parts": {+ "symbol": "tps51220arsnt.kicad_sym",+ "footprint": "tps51220arsnt.kicad_mod",+ "model_3d": "tps51220arsnt-hero.glb",+ "model_3d_plain": "tps51220arsnt.glb",+ "model_3d_step": "tps51220arsnt-etched.step",+ "model_3d_step_plain": "tps51220arsnt.step",+ "lbr": "tps51220arsnt.lbr"+ },+ "distributor_links": {+ "lcsc": "C2658965",+ "digikey": "296-25541-2-ND",+ "mouser": "595-TPS51220ARSNT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:51:17Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-25541-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS51220ARSNT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DRVH1",+ "type": "output",+ "description": "Channel 1 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node-referenced floating driver with drive voltage equal to VBST-to-SW."+ },+ {+ "number": "2",+ "name": "V5SW",+ "type": "input",+ "description": "5-V switchover supply input; when EN1 is high, PGOOD1 indicates good and V5SW is above 4.8 V, VREG5 switches over to V5SW."+ },+ {+ "number": "3",+ "name": "RF",+ "type": "bidirectional",+ "description": "Frequency setting pin: connect a frequency-setting resistor to GND, or an external clock for synchronization; the fixed frequency is adjustable from 200 kHz to 1 MHz."+ },+ {+ "number": "4",+ "name": "EN1",+ "type": "input",+ "description": "Channel 1 SMPS enable; apply greater than 0.55 V and less than 6 V to turn on or leave floating, connect to GND to disable, and the adjustable soft-start capacitor attaches here."+ },+ {+ "number": "5",+ "name": "PGOOD1",+ "type": "output",+ "description": "Channel 1 powergood window comparator output; recommended applied voltage less than 6 V and recommended pull-up resistor 100 kΩ to 1 MΩ."+ },+ {+ "number": "6",+ "name": "SKIPSEL1",+ "type": "input",+ "description": "Channel 1 skip mode selection: GND selects continuous conduction, VREF2 auto skip, VREG3 OOA auto skip (max 7 skips, suitable for fsw < 400 kHz), VREG5 OOA auto skip (max 15 skips, suitable for fsw ≥ 400 kHz)."+ },+ {+ "number": "7",+ "name": "CSP1",+ "type": "bidirectional",+ "description": "Channel 1 current sense comparator positive input; an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop, 0.1 µF suggested as a starting value."+ },+ {+ "number": "8",+ "name": "CSN1",+ "type": "input",+ "description": "Channel 1 current sense comparator negative input, also the supply for the current sense circuit at 5 V or higher output settings and the output discharge terminal."+ },+ {+ "number": "9",+ "name": "VFB1",+ "type": "input",+ "description": "Channel 1 SMPS voltage feedback input, connected to the feedback resistor divider and referred to signal GND; regulation voltage 1.000 V nominal."+ },+ {+ "number": "10",+ "name": "COMP1",+ "type": "input",+ "description": "Channel 1 loop compensation pin for current mode (error amplifier output), connect R (and C if required) to VREF2; in D-CAP mode, R to VREF2 sets ramp compensation, 10 kΩ suggested (6 kΩ to 20 kΩ)."+ },+ {+ "number": "11",+ "name": "FUNC",+ "type": "input",+ "description": "Control architecture and OVP selection: GND for current mode with OVP enabled, VREF2 for D-CAP mode with OVP disabled, VREG3 for D-CAP mode with OVP enabled, VREG5 for current mode with OVP disabled."+ },+ {+ "number": "12",+ "name": "EN",+ "type": "input",+ "description": "VREF2 and VREG5 linear regulator enable; apply greater than 1.2 V and less than 6 V to turn on, connect to GND to disable."+ },+ {+ "number": "13",+ "name": "VREF2",+ "type": "output",+ "description": "2-V reference output, to be bypassed to signal GND with 0.22 µF of ceramic capacitance."+ },+ {+ "number": "14",+ "name": "TRIP",+ "type": "input",+ "description": "Overcurrent trip level and discharge mode selection: GND gives V(OCL-ULV) with discharge on, VREF2 gives V(OCL-ULV) with discharge off, VREG3 gives V(OCL-LV) with discharge off, VREG5 gives V(OCL-LV) with discharge on."+ },+ {+ "number": "15",+ "name": "COMP2",+ "type": "input",+ "description": "Channel 2 loop compensation pin for current mode (error amplifier output), connect R (and C if required) to VREF2; in D-CAP mode, R to VREF2 sets ramp compensation, 10 kΩ suggested (6 kΩ to 20 kΩ)."+ },+ {+ "number": "16",+ "name": "VFB2",+ "type": "input",+ "description": "Channel 2 SMPS voltage feedback input, connected to the feedback resistor divider and referred to signal GND."+ },+ {+ "number": "17",+ "name": "CSN2",+ "type": "input",+ "description": "Channel 2 current sense comparator negative input, also the supply for the current sense circuit at 5 V or higher output settings and the output discharge terminal."+ },+ {+ "number": "18",+ "name": "CSP2",+ "type": "bidirectional",+ "description": "Channel 2 current sense comparator positive input; an RC network with X5R or X7R ceramic capacitor extracts the DCR voltage drop, 0.1 µF suggested as a starting value."+ },+ {+ "number": "19",+ "name": "SKIPSEL2",+ "type": "input",+ "description": "Channel 2 skip mode selection: GND selects continuous conduction, VREF2 auto skip, VREG3 OOA auto skip (max 7 skips, suitable for fsw < 400 kHz), VREG5 OOA auto skip (max 15 skips, suitable for fsw ≥ 400 kHz)."+ },+ {+ "number": "20",+ "name": "PGOOD2",+ "type": "output",+ "description": "Channel 2 powergood window comparator output; recommended applied voltage less than 6 V and recommended pull-up resistor 100 kΩ to 1 MΩ."+ },+ {+ "number": "21",+ "name": "EN2",+ "type": "input",+ "description": "Channel 2 SMPS enable; apply greater than 0.55 V and less than 6 V to turn on or leave floating, connect to GND to disable, and the adjustable soft-start capacitor attaches here."+ },+ {+ "number": "22",+ "name": "VREG3",+ "type": "output",+ "description": "Always-alive 3.3-V, 10-mA low-dropout linear regulator output, bypass to signal GND with more than 1 µF ceramic; runs from VIN or from VREG5 when switched over to V5SW."+ },+ {+ "number": "23",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input for the 5-V and 3.3-V linear regulators, typically connected to VBAT; input range 4.5 V to 32 V."+ },+ {+ "number": "24",+ "name": "DRVH2",+ "type": "output",+ "description": "Channel 2 high-side MOSFET gate driver output, source 1.7 Ω and sink 1.0 Ω, SW-node-referenced floating driver with drive voltage equal to VBST-to-SW."+ },+ {+ "number": "25",+ "name": "SW2",+ "type": "bidirectional",+ "description": "Channel 2 high-side MOSFET gate driver return (switch node), referenced for the floating high-side driver."+ },+ {+ "number": "26",+ "name": "VBST2",+ "type": "input",+ "description": "Channel 2 bootstrap supply input for the high-side N-channel FET driver; connect a capacitor of 0.1 µF or greater from this pin to SW2, an additional Schottky diode from VREG5 is optional."+ },+ {+ "number": "27",+ "name": "DRVL2",+ "type": "output",+ "description": "Channel 2 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver."+ },+ {+ "number": "28",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "29",+ "name": "VREG5",+ "type": "output",+ "description": "5-V, 100-mA low-dropout linear regulator output, bypass to power GND with 10 µF ceramic; runs from VIN and switches over to V5SW when 4.8 V or above is provided."+ },+ {+ "number": "30",+ "name": "DRVL1",+ "type": "output",+ "description": "Channel 1 low-side MOSFET gate driver output, source 1.3 Ω and sink 0.7 Ω, GND-referenced driver."+ },+ {+ "number": "31",+ "name": "VBST1",+ "type": "input",+ "description": "Channel 1 bootstrap supply input for the high-side N-channel FET driver; connect a capacitor of 0.1 µF or greater from this pin to SW1, an additional Schottky diode from VREG5 is optional."+ },+ {+ "number": "32",+ "name": "SW1",+ "type": "bidirectional",+ "description": "Channel 1 high-side MOSFET gate driver return (switch node), referenced for the floating high-side driver."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet shows an exposed PowerPAD on the QFN-32 package but gives no pin number for it in the ; The I/O column of the PIN FUNCTIONS table was partly lost in text extraction, so some pin types were; The RSN top-view drawing text in the extraction is scrambled, so the pin numbers come from the PIN F",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.1071,+ "at": "2026-10-08T15:51:02"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps51220a",+ "pages": 55,+ "sha256": "6e980b37451f3708",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps51220arsnt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.6+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7b482a511cdf2cf875c31931f9fea7f745b8dac2ea6203531cd6604f40a290cb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps51220arsnt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.6+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4db719806c49236cbf86320f5029519130cdd096b349d592acfcaeed030a1f12",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}