component

TPS51219RTET

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS51219RTET

Texas Instruments · DC-DC Converters · QFN-16-EP(3x3)

TPS51219RTET from Texas Instruments, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in 2.0-V ±0.8% internal voltage reference output with 300-µA drive capability for external resistor divider network.
2 REFIN input Output voltage setting input programmed by resistor divider connected between VREF and GSNS within 0.5V to 2.0V range.
3 GSNS input GND sense return input connected to quiet ground reference point of load; short to GND if remote sensing not used.
4 VSNS input Voltage sense input connected to load voltage point for differential remote voltage feedback to error amplifier.
5 COMP input Error amplifier output and compensation network connection point; capacitor connected from COMP to VSNS (D-CAP2) or output capacitor (D-CAP).
6 TRIP input Overcurrent threshold setting input sourcing 10µA at room temperature with 4700ppm/°C temperature coefficient for RDS(on) current sensing configuration.
7 GND power_in Device analog ground reference; connect to quiet point on system ground plane with multiple vias.
8 PGND power_in Power ground return for low-side synchronous MOSFET gate driver and positive input for current sensing; route close to device.
9 V5 power_in 5V power supply input for internal circuits and MOSFET gate drivers; operating range 4.2V to 5.5V.
10 DL output Low-side synchronous MOSFET gate driver output; directly drives gate of low-side power FET.
11 DH output High-side synchronous MOSFET gate driver output; directly drives gate of high-side power FET with bootstrap charge.
12 SW bidirectional Switching node connection for high-side gate driver return and RDS(on) current sense negative input referenced to PGND.
13 BST input Bootstrap gate drive supply input for high-side driver; connect storage capacitor between BST and SW pins.
14 EN input Enable control input with 3.3V I/O level compatibility and 100ns debounce; short to GND to disable device operation.
15 MODE input Control mode selection input; resistor tied to GND sets D-CAP™/D-CAP2™ mode, switching frequency (300-670kHz), and current sensing scheme.
16 PGOOD tri_state Open-drain power good output signal; asserts high when output voltage within ±8% (typ) of REFIN target range.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TPS51219RTET
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps51219rtet-etched.step / tps51219rtet-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps51219rtet.step / tps51219rtet.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 d6e730c2602800ae, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF