# TPS51217DSCR

**Texas Instruments** · DC-DC Controllers · WSON-10-EP(3x3)

TPS51217DSCR from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGOOD | output | Power-good window comparator open-drain output that needs a pull-up to 5 V or an appropriate signal voltage, with continuous current capability of 1 mA; it goes high 1 ms after VFB is within limits and goes low after a 2-µs delay when VFB leaves the limits. |
| 2 | TRIP | input | Overcurrent-limit (OCL) detection threshold setting pin, which sources 10 µA at room temperature with a 4700 ppm/°C coefficient to set the OCL trip voltage for 0.2 V ≤ V(TRIP) ≤ 3 V. |
| 3 | EN | input | SMPS enable pin; short it to GND to disable the device, with enable threshold of 1.8 V and disable threshold of 0.5 V. |
| 4 | VFB | input | SMPS feedback input to which the feedback resistor divider is connected, regulating to the 0.6 V internal reference. |
| 5 | TRAN | input | Dynamic voltage change control pin that forces CCM and masks PGOOD, OVP and UVP when pulled up or pulled down, with masking ending 900 µs after TRAN returns to normal; leave it open when dynamic voltage change is not used. |
| 6 | DRVL | output | Synchronous MOSFET driver output referenced to GND, with gate drive voltage defined by the V5IN voltage. |
| 7 | V5IN | power_in | 5 V supply input that accepts +30% / -10% variation (4.5 V to 6.5 V recommended operating range). |
| 8 | SW | input | Switch node that serves as the high-side MOSFET gate drive return and is also used for on-time generation and output discharge; SW may see -1 V to 28 V in recommended operation. |
| 9 | DRVH | output | High-side MOSFET driver output referenced to the floating SW node, with gate drive voltage defined by the voltage across the VBST-to-SW bootstrap flying capacitor. |
| 10 | VBST | input | Supply input for the high-side driver (bootstrap terminal) that connects to a flying capacitor to the SW pin and is internally connected to V5IN through the bootstrap MOSFET switch. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage V5IN | V5IN | 4.5 |  | 6.5 | V |  | 3 |
| VBST voltage range | VBST | -0.1 |  | 34.5 | V |  | 3 |
| SW input voltage range | SW | -1 |  | 28 | V |  | 3 |
| SW input voltage range (transient) | SW(1) | -4 |  | 28 | V | This voltage should be applied for less than 30% of the repetitive period | 3 |
| VBST voltage range (vs SW) | VBST(2) | -0.1 |  | 6.5 | V | Voltage values are with respect to the SW terminal | 3 |
| EN, TRIP, VFB, TRAN voltage range |  | -0.1 |  | 6.5 | V |  | 3 |
| DRVH output voltage range | DRVH | -1 |  | 34.5 | V |  | 3 |
| DRVH output voltage range (transient) | DRVH(1) | -4 |  | 34.5 | V | This voltage should be applied for less than 30% of the repetitive period | 3 |
| DRVH output voltage range (vs SW) | DRVH(2) | -0.1 |  | 6.5 | V | Voltage values are with respect to the SW terminal | 3 |
| DRVL output voltage range | DRVL | -0.3 |  | 6.5 | V |  | 3 |
| PGOOD output voltage range | PGOOD | -0.1 |  | 6.5 | V |  | 3 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 3 |
| VBST input voltage range | VBST | -0.3 |  | 37 | V | With respect to network ground | 2 |
| VBST voltage (vs SW) | VBST(3) | -0.3 |  | 7 | V | With respect to SW terminal | 2 |
| SW input voltage range | SW | -5 |  | 30 | V | With respect to network ground | 2 |
| V5IN, EN, TRIP, VFB, TRAN input voltage range |  | -0.3 |  | 7 | V | With respect to network ground | 2 |
| DRVH output voltage range | DRVH | -5 |  | 37 | V | With respect to network ground | 2 |
| DRVH output voltage (vs SW) | DRVH(3) | -0.3 |  | 7 | V | With respect to SW terminal | 2 |
| DRVH output voltage, pulse width < 20 ns | DRVH | -2.5 |  | 7 | V | Pulse width < 20 ns; with respect to SW terminal | 2 |
| DRVL output voltage range | DRVL | -0.5 |  | 7 | V |  | 2 |
| DRVL output voltage, pulse width < 20 ns | DRVL | -2.5 |  | 7 | V | Pulse width < 20 ns | 2 |
| PGOOD output voltage range | PGOOD | -0.3 |  | 7 | V |  | 2 |
| Junction temperature range | TJ |  |  | 150 | °C |  | 2 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 2 |
| V5IN supply current | I(V5IN) |  | 320 | 500 | µA | TA = 25°C, No Load, V(EN) = 5 V, V(VFB) = 0.63 V | 3 |
| V5IN shutdown current | ISD(V5IN) |  |  | 1 | µA | TA = 25°C, No Load, V(EN) = 0 V | 3 |
| VFB regulation voltage | V(VFB) | 0.6 | 0.603 | 0.606 | V | TA = 25°C, skip mode | 3 |
| VFB regulation voltage | V(VFB) | 0.5974 | 0.603 | 0.6086 | V | TA = 0°C to 85°C, skip mode | 3 |
| VFB regulation voltage | V(VFB) | 0.596 | 0.603 | 0.61 | V | TA = –40°C to 85°C, skip mode | 3 |
| Output discharge current from SW pin | IDischg |  | 5 | 13 | mA | V(EN) = 0 V, V(SW) = 0.5 V | 3 |
| DRVH resistance, source | R(DRVH) |  | 1.5 | 3 | Ω | Source, I(DRVH) = –50 mA | 3 |
| DRVH resistance, sink | R(DRVH) |  | 0.7 | 1.8 | Ω | Sink, I(DRVH) = 50 mA | 3 |
| DRVL resistance, source | R(DRVL) |  | 1 | 2.2 | Ω | Source, I(DRVL) = –50 mA | 3 |
| DRVL resistance, sink | R(DRVL) |  | 0.5 | 1.2 | Ω | Sink, I(DRVL) = 50 mA | 3 |
| Dead time, DRVH-off to DRVL-on | tD | 7 | 17 | 30 | ns | DRVH-off to DRVL-on | 3 |
| Dead time, DRVL-off to DRVH-on | tD | 10 | 22 | 35 | ns | DRVL-off to DRVH-on | 3 |
| Minimum off-time | tOFF(min) | 150 | 260 | 400 | ns | TA = 25°C | 3 |
| Switching frequency | fSW | 312 | 340 | 368 | kHz | TA = 25°C | 3 |
| PG threshold, PG in from lower | V(THPG) | 92.5 | 95 | 97.5 | % | PG in from lower | 4 |
| PG threshold, PG in from higher | V(THPG) | 107.5 | 110 | 112.5 | % | PG in from higher | 4 |
| PG delay | tPGDEL | 0.8 | 1 | 1.2 | ms | Delay for PG in | 4 |
| EN enable voltage | V(EN) | 1.8 |  |  | V | Enable | 4 |
| EN disable voltage | V(EN) |  |  | 0.5 | V | Disable | 4 |
| TRAN voltage, TRAN open | V(TRAN) | 1.83 | 1.88 | 1.93 | V | TRAN open | 4 |
| TRAN voltage, mask PG/OVP/UVP high side | V(TRAN) | 2.03 | 2.08 | 2.13 | V | Mask PG, OVP and UVP, high side | 4 |
| TRAN voltage, mask PG/OVP/UVP low side | V(TRAN) | 1.62 | 1.67 | 1.72 | V | Mask PG, OVP and UVP, low side | 4 |
| TRIP source current | I(TRIP) | 9 | 10 | 11 | µA | V(TRIP) = 1 V, TA = 25°C | 4 |
| Current limit threshold | VOCL | 355 | 375 | 395 | mV | V(TRIP) = 3 V | 4 |
| Current limit threshold | VOCL | 185 | 200 | 215 | mV | V(TRIP) = 1.6 V | 4 |
| Current limit threshold | VOCL | 17 | 25 | 33 | mV | V(TRIP) = 0.2 V | 4 |
| Negative current limit threshold | VOCLN | -395 | -375 | -355 | mV | V(TRIP) = 3 V | 4 |
| Negative current limit threshold | VOCLN | -215 | -200 | -185 | mV | V(TRIP) = 1.6 V | 4 |
| Negative current limit threshold | VOCLN | -33 | -25 | -17 | mV | V(TRIP) = 0.2 V | 4 |
| OVP trip threshold | V(OVP) | 115 | 120 | 125 | % | OVP detect | 4 |
| UVP trip threshold | V(UVP) | 65 | 70 | 75 | % | UVP detect | 4 |
| V5IN UVLO wake-up threshold |  | 4.2 | 4.38 | 4.5 | V | Wake up | 4 |
| V5IN UVLO shutdown threshold |  | 3.7 | 3.93 | 4.1 | V | Shutdown | 4 |
| Thermal shutdown threshold | TSDN |  | 145 |  | °C | Specified by design. Not production tested. | 4 |
| I(TRIP) temperature coefficient | I(TRIP) |  | 4700 |  | ppm/°C | On the basis of 25°C | 4 |
| Package power derating factor |  |  | 15 |  | mW/°C | Above TA = 25°C | 2 |

## CAD (KiCad official)

- Symbol: `TPS51217DSCR`
- Footprint: `Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm`
- 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `tps51217dscr-etched.step` / `tps51217dscr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps51217dscr.step` / `tps51217dscr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps51217) (30 pp, sha256 `570e4a6cca99822c`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps51217dscr-datasheet.pdf)