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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS51120RHBR

Texas Instruments · AC-DC Controllers And Regulators · TQFN-32-EP(5x5)

TPS51120RHBR from Texas Instruments, in a TQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VO1	input	Output voltage node serving on-time adjustment, output discharge, switchover, and feedback functions; connect to positive terminal of SMPS output capacitor.
2	COMP1	output	Loop compensation pin (error amplifier output); connect RC network to GND for current mode or tie to V5FILT for D-CAP mode.
3	VFB1	input	SMPS feedback input; connect feedback resistor divider here for adjustable outputs or tie to V5FILT for fixed option.
4	VREF2	output	2-V reference output, ±50-μA, ±2% over 0-85°C; bypass to GND with 1-nF ceramic capacitor.
5	GND	power_in	Signal ground pin.
6	VFB2	input	SMPS feedback input; connect feedback resistor divider here for adjustable outputs or tie to V5FILT for fixed option.
7	COMP2	output	Loop compensation pin (error amplifier output); connect RC network to GND for current mode or tie to V5FILT for D-CAP mode.
8	VO2	input	Output voltage node serving on-time adjustment, output discharge, switchover, and feedback functions; connect to positive terminal of SMPS output capacitor.
9	EN5	input	5-V regulator enable pin; connect to GND to disable or float/tie to VBAT to enable with 3-ms soft-start.
10	EN3	input	3.3-V regulator enable pin; connect to GND to disable or float/tie to VREG5 to enable.
11	PGOOD2	output	Power-good window comparator open drain output; 5-mA pull-up capability with 1-ms high and 10-μs low response.
12	EN2	input	Channel 2 SMPS enable pin with 3-ms internal soft-start; external capacitor to ground programs slower ramp rate.
13	VBST2	power_in	High-side driver supply input; connect capacitor from this pin to LL2 with internal PN diode from VREG5.
14	DRVH2	output	High-side MOSFET gate driver output; source 3.5Ω, sink 1.5Ω, floating from LL with voltage corresponding to VBST-to-LL.
15	LL2	bidirectional	High-side gate driver return; also serves as current sense negative input and input voltage monitor for on-time control.
16	DRVL2	output	Low-side MOSFET gate driver output; source 3.5Ω, sink 1.5Ω, PGND referenced with VREG5 drive voltage.
17	PGND2	power_in	Ground return for low-side gate driver; also serves as current sense positive input and must be tied with PGND1 and GND.
18	CS2	input	Current sense comparator negative input for resistor sensing or overcurrent trip setting via V5FILT threshold resistor.
19	VREG3	power_out	3.3-V, 100-mA linear regulator output; bypass with 10-μF ceramic to PGND and switches to VO2 above 3.1V.
20	V5FILT	power_in	5-V control circuit supply input; derive from VREG5 via RC filter for clean supply.
21	VREG5	power_out	5-V, 100-mA linear regulator output; bypass with 10-μF ceramic, internally connected to VBST and DRVL drivers.
22	VIN	power_in	Supply input for 5-V and 3.3-V linear regulators; typically connected to VBAT with 4.5-28V operating range.
23	CS1	input	Current sense comparator negative input for resistor sensing or overcurrent trip setting via V5FILT threshold resistor.
24	PGND1	power_in	Ground return for low-side gate driver; also serves as current sense positive input and must be tied with PGND2 and GND.
25	DRVL1	output	Low-side MOSFET gate driver output; source 3.5Ω, sink 1.5Ω, PGND referenced with VREG5 drive voltage.
26	LL1	bidirectional	High-side gate driver return; also serves as current sense negative input and input voltage monitor for on-time control.
27	DRVH1	output	High-side MOSFET gate driver output; source 3.5Ω, sink 1.5Ω, floating from LL with voltage corresponding to VBST-to-LL.
28	VBST1	power_in	High-side driver supply input; connect capacitor from this pin to LL1 with internal PN diode from VREG5.
29	EN1	input	Channel 1 SMPS enable pin with 3-ms internal soft-start; external capacitor to ground programs slower ramp rate.
30	PGOOD1	output	Power-good window comparator open drain output; 5-mA pull-up capability with 1-ms high and 10-μs low response.
31	TONSEL	input	On-time selection pin for programming; refer to Table 1 and Table 5 for configuration options.
32	SKIPSEL	input	Skip and fault mode selection pin for programming; refer to Table 5 for configuration options.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFN-32-EP(5x5)
Category	Power Management (PMIC)
Pins	33

CAD (KiCad official)

Symbol: TPS51120RHBR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: TQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: tps51120rhbr-etched.step / tps51120rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps51120rhbr.step / tps51120rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 6804e33e2b019f27, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF