component
TPS51116RGER
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS51116RGER
Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)
TPS51116RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VTTGND | power_in | Power return for VTT LDO output. |
| 2 | VTTSNS | input | VTT output voltage sense input connected to positive node of output capacitor. |
| 3 | GND | power_in | Signal ground for VTT reference circuits. |
| 4 | MODE | input | Discharge mode selection pin; V5IN for no discharge, VDDQ for tracking, GND for non-tracking. |
| 5 | VTTREF | output | Buffered reference output providing VVDDQSNS/2 ±20mV at ±10mA output current. |
| 6 | COMP | bidirectional | Transconductance amplifier output for current mode compensation or D-CAP mode feedback. |
| 7 | NC | unconnected | No connection; pin not used internally. |
| 8 | VDDQSNS | bidirectional | VDDQ reference and feedback input for VTT LDO and VTTREF generation. |
| 9 | VDDQSET | input | VDDQ output voltage setting; GND for 2.5V, V5FILT for 1.8V, external divider for 0.75-3.0V. |
| 10 | S3 | input | S3 sleep mode input; LOW puts VTT in high-Z, HIGH enables normal operation. |
| 11 | S5 | input | S5 sleep mode input; LOW in S4/S5 states triggers discharge of all outputs. |
| 12 | NC | unconnected | No connection; pin not used internally. |
| 13 | PGOOD | output | Powergood open-drain output; HIGH when VDDQ is 95%-105% of target voltage. |
| 14 | V5FILT | power_in | Filtered 5V supply input for internal circuits; bypass with 1.0-4.7μF ceramic capacitor. |
| 15 | V5IN | power_in | 5V supply input for internal circuits and gate drivers; bypass with 1.0-4.7μF capacitor. |
| 16 | CS | bidirectional | Current sense comparator input for resistor-sense or RDS(on)-sense schemes. |
| 17 | CS_GND | power_in | Current sense comparator ground and powergood circuit return path. |
| 18 | PGND | power_in | Power ground for low-side gate driver; use ≥0.65mm trace width. |
| 19 | DRVL | output | Low-side MOSFET gate driver output with 3Ω source and 0.9Ω sink impedance. |
| 20 | LL | bidirectional | High-side gate driver return and RDS(on) current sense input node. |
| 21 | DRVH | output | High-side MOSFET gate driver output with 3Ω source and 0.9Ω sink impedance. |
| 22 | VBST | bidirectional | Bootstrap supply input for high-side driver; voltage range -0.1V to 34V. |
| 23 | VLDOIN | power_in | VTT LDO supply input; 1.5V to 3.6V for reduced dissipation or tied to VDDQ. |
| 24 | VTT | power_out | VTT LDO output providing ±3A source/sink with ±40mV regulation to 20μF ceramic. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
TPS51116RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps51116rger-etched.step/tps51116rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps51116rger.step/tps51116rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
f9e2fd18700b05c2, retrieved 2026-09-24, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).