TPS51116PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VLDOIN	input	Power supply input for the VTT LDO, with a recommended range of -0.1 V to 3.6 V and an absolute maximum of 6 V.
2	VTT	power_out	Power output of the VTT LDO, which can sink and source 3 A and requires 20 µF (2 × 10 µF) of ceramic output capacitance.
3	VTTGND	power_in	Power ground output for the VTT LDO, with a recommended range of -0.1 V to 0.1 V.
4	VTTSNS	input	Voltage sense input for the VTT LDO, which connects to the plus terminal of the VTT LDO output capacitor, with a recommended range of -0.1 V to 3.6 V.
5	GND	power_in	Signal ground, which connects to the negative terminal of the VTT LDO output capacitor.
6	MODE	input	Discharge mode setting pin: V5IN selects no discharge, VDDQ selects tracking discharge, and GND selects non-tracking discharge, with a recommended range of -0.1 V to 5.25 V.
7	VTTREF	output	Buffered VTTREF reference output rated for ±10 mA, with a recommended range of -0.1 V to 1.8 V.
8	COMP	bidirectional	Output of the transconductance amplifier for phase compensation; connecting it to V5IN disables the gM amplifier and selects D-CAP mode, with a recommended range of -0.1 V to 5.25 V.
9	VDDQSNS	bidirectional	VDDQ reference input for VTT and VTTREF, power supply for VTTREF, and output voltage feedback input when VDDQSET is connected to V5IN or GND, with a recommended range of -0.1 V to 3.6 V.
10	VDDQSET	input	VDDQ output voltage setting pin, with a recommended range of -0.1 V to 5.25 V.
11	S3	input	S3 signal input, with a recommended range of -0.1 V to 5.25 V.
12	S5	input	S5 signal input, with a recommended range of -0.1 V to 5.25 V.
13	PGOOD	output	Powergood open-drain output that is high when the VDDQ output is within its target range, with a recommended range of -0.1 V to 5.25 V.
14	V5IN	input	5-V power supply input for the internal circuits and MOSFET gate drivers, with a recommended supply range of 4.75 V to 5.25 V.
15	CS	bidirectional	Current sense comparator input (-) for resistor current sensing, or overcurrent trip voltage setting input for RDS(on) sensing when connected to V5IN through a voltage setting resistor, with a recommended range of -0.1 V to 5.25 V.
16	PGND	power_in	Ground for the low-side MOSFET gate driver, and also the current sense comparator input (+) and powergood circuit ground in the PWP package, with a recommended range of -0.1 V to 0.1 V.
17	DRVL	output	Rectifying (low-side) MOSFET gate-drive output, with a recommended range of -0.1 V to 5.25 V.
18	LL	bidirectional	Switching (high-side) MOSFET gate driver return and current sense comparator input (-) for RDS(on) sensing, with a recommended range of -0.6 V to 28 V.
19	DRVH	output	Switching (high-side) MOSFET gate-drive output, with a recommended range of -0.1 V to 34 V.
20	VBST	bidirectional	Bootstrap voltage input for the switching (high-side) MOSFET driver, with a recommended range of -0.1 V to 34 V and an absolute maximum of 6 V relative to LL.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-20-EP
Category	Power Management ICs
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage range, VBST	VIN	-0.3		36	V		4
VBST wrt LL		-0.3		6	V		4
Voltage range, CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET, V5FILT		-0.3		6	V		4
Voltage range, PGND, VTTGND, CS_GND		-0.3		0.3	V		4
Output voltage range, DRVH	VOUT	-1		36	V		4
Output voltage range, LL	VOUT	-1		30	V		4
Output voltage range, COMP, DRVL, PGOOD, VTT, VTTREF	VOUT	-0.3		6	V		4
Operating ambient temperature range	TA	-40		85	°C		4
Storage temperature	Tstg	-55		150	°C		4
Supply voltage, V5IN, V5FILT		4.75		5.25	V		4
Voltage range, VBST, DRVH		-0.1		34	V		4
Voltage range, LL		-0.6		28	V		4
Voltage range, VLDOIN, VTT, VTTSNS, VDDQSNS		-0.1		3.6	V		4
Voltage range, VTTREF		-0.1		1.8	V		4
Voltage range, PGND, VTTGND, CS_GND		-0.1		0.1	V		4
Voltage range, S3, S5, MODE, VDDQSET, CS, COMP, PGOOD, DRVL		-0.1		5.25	V		4
Operating free-air temperature	TA	-40		85	°C		4
Supply current 1, V5IN	IV5IN1		0.8	2	mA	TA = 25°C, No load, VS3 = VS5 = 5 V, COMP connected to capacitor	5
Supply current 2, V5IN	IV5IN2		300	600	µA	TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, COMP connected to capacitor	5
Shutdown current, V5IN	IV5INSDN		0.1	1	µA	TA = 25°C, No load, VS3 = VS5 = 0 V	5
Output voltage tolerance to VVDDQSNS/2, VTTREF (2.5 V)	VVTTREFTOL	-20		20	mV	-10 mA < IVTTREF < 10 mA, VVDDQSNS = 2.5 V	5
Output voltage tolerance to VVDDQSNS/2, VTTREF (1.8 V)	VVTTREFTOL	-18		18	mV	-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.8 V	5
Source current, VTTREF	VVTTREFSRC	-20	-40	-80	mA	VVDDQSNS = 2.5 V, VVTTREF = 0 V	5
Sink current, VTTREF	VVTTREFSNK	20	40	80	mA	VVDDQSNS = 2.5 V, VVTTREF = 2.5 V	5
Output voltage, VDDQ	VVDDQ	2.465	2.5	2.535	V	TA = 25°C, VVDDQSET = 0 V, No load	6
Output voltage, VDDQ	VVDDQ	2.44	2.5	2.55	V	-40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load	6
Output voltage, VDDQ	VVDDQ	1.776	1.8	1.824	V	TA = 25°C, VVDDQSET = 5 V, No load	6
Output voltage, VDDQ	VVDDQ	1.764	1.8	1.836	V	-40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load	6
Output voltage, VDDQ adjustable mode		0.75		3	V	-40°C ≤ TA ≤ 85°C, Adjustable mode, No load	6
VDDQSET regulation voltage	VVDDQSET	742.5	750	757.5	mV	TA = 25°C, Adjustable mode	6
Discharge current, VDDQ	IVDDQDisch	10		40	mA	VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, VMODE = 0 V	6
VTT output voltage tolerance to VTTREF (2.5 V)	VVTTTOL25	-20		20	mV	VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, IVTT = 0 A	6
VTT output voltage tolerance to VTTREF (2.5 V)	VVTTTOL25	-40		40	mV	VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, /IVTT/ < 3 A	6
Source current limit, VTT	IVTTOCLSRC	3	3.8	6	A	VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.19 V, PGOOD = HI	6
Sink current limit, VTT	IVTTOCLSNK	3	3.6	6	A	VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.31 V, PGOOD = HI	6
Discharge current, VTT	IVTTDisch	10		17	mA	TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V, VVTT = 0.5 V	7
Input bias current, VTTSNS	IVTTBIAS	-1	-0.1	1	µA	VS3 = 5 V, VVTTSNS = VVDDQSNS /2	7
Gain, transconductance amplifier	gm	240	300	360	µS	TA = 25°C	7
COMP high clamp voltage	VCOMPHI	1.31	1.34	1.37	V	VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCS = 0 V	7
COMP low clamp voltage	VCOMPLO	1.18	1.21	1.24	V	VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCS = 0 V	7
Zero current comparator offset	VZC	-6	0	6	mV		7
DRVH resistance, source	RDRVH		3	6	Ω	Source, IDRVH = -100 mA	7
DRVH resistance, sink	RDRVH		0.9	3	Ω	Sink, IDRVH = 100 mA	7
Forward voltage, internal BST diode	VFBST	0.7	0.8	0.9	V	VV5IN-VBST , IF = 10 mA, TA = 25°C	7
VBST leakage current	IVBSTLK		0.1	1	µA	VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V, TA = 25°C	7
Current limit threshold, PGOOD = HI	VOCL	50	60	70	mV	VPGND-CS , PGOOD = HI, VCS < 0.5 V	8
Current sense sink current, PGOOD = HI	ITRIP	9	10	11	µA	TA = 25°C, VCS > 4.5 V, PGOOD = HI	8
Overcurrent protection COMP offset	VOCL(off)	-5	0	5	mV	(VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV, VCS > 4.5 V	8
Current limit threshold setting range	VR(trip)	30		150		VV5IN-CS	8
VDDQ powergood threshold, PG in from lower	VTVDDQPG	92.5	95	97.5	%	PG in from lower	8
VDDQ powergood threshold, PG in from higher	VTVDDQPG	102.5	105	107.5	%	PG in from higher	8
PGOOD delay time	tPG(del)	80	130	200	µs	Delay for PG in	8
PGOOD sink current	IPG(max)	2.5		7.5	mA	VVTT = 0 V, VPGOOD = 0.5 V	8
V5IN UVLO threshold voltage, wake up	VUVV5IN	3.7	4	4.3	V	Wake up	8
V5IN UVLO threshold voltage, hysteresis	VUVV5IN	0.2	0.3	0.4	V	Hysteresis	8
VDDQSET threshold voltage, 2.5 V output	VTHVDDQSET	0.08	0.15	0.25		2.5 V output	8
VDDQSET threshold voltage, 1.8 V output	VTHVDDQSET	3.5	4	4.5		1.8 V output	8
Logic input leakage current, S3, S5, MODE	VINLEAK	-1		1	µA	S3, S5, MODE	8
VDDQ OVP trip threshold voltage, OVP detect	VOVP	110	115	120	%	OVP detect	8
Junction-to-ambient thermal resistance, PWP 20-pin HTSSOP	RθJA		41.2		°C/W	PWP 20-pin HTSSOP package	5

CAD (KiCad official)

Symbol: TPS51116PWPR
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: tps51116pwpr-etched.step / tps51116pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps51116pwpr.step / tps51116pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (49 pp, sha256 226d379a4865de90, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPS51116PWPR

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3D Model

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