component
TPS51116PWP
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS51116PWP
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
TPS51116PWP from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VLDOIN | input | Power supply input for the VTT LDO, which should be connected to the VDDQ output when tracking discharge mode is used. |
| 2 | VTT | output | Power output of the VTT LDO, which can sink and source 3 A. |
| 3 | VTTGND | power_in | Power ground output for the VTT LDO. |
| 4 | VTTSNS | input | Voltage sense input for the VTT LDO, to be connected to the plus terminal of the VTT LDO output capacitor. |
| 5 | GND | power_in | Signal ground, to be connected to the negative terminal of the VTT LDO output capacitor. |
| 6 | MODE | input | Discharge mode setting pin, where tying it to V5IN selects no discharge, to VDDQ selects tracking discharge and to GND selects non-tracking discharge. |
| 7 | VTTREF | output | Buffered VTTREF reference output, which supplies a low noise 10-mA VREF with a tolerance of ±20 mV. |
| 8 | COMP | bidirectional | Output of the transconductance amplifier for phase compensation, connected to V5IN to disable the gM amplifier and use D-CAP mode. |
| 9 | VDDQSNS | bidirectional | VDDQ reference input for VTT and VTTREF and output voltage feedback input for VDDQ when VDDQSET is tied to V5IN or GND, and the non-tracking discharge current sink terminal. |
| 10 | VDDQSET | input | VDDQ output voltage setting pin, which is connected to a resistor divider to set the output voltage or to V5IN or GND for internal setting. |
| 11 | S3 | input | S3 signal input that places VTT at high-Z in suspend-to-RAM state. |
| 12 | S5 | input | S5 signal input that enables the SMPS and LDO outputs and controls soft-off in S4/S5 states. |
| 13 | PGOOD | output | Powergood open-drain output that is high when the VDDQ output voltage is within the target range. |
| 14 | V5IN | input | 5-V power supply input for internal circuits and MOSFET gate drivers, with an operating range of 4.75 V to 5.25 V. |
| 15 | CS | input | Current sense comparator input (-) for resistor current sensing, or overcurrent trip voltage setting input for RDS(on) sensing when connected to V5IN through a voltage setting resistor. |
| 16 | PGND | power_in | Ground for the low-side MOSFET gate driver, and also the current sense comparator input (+) and ground for the powergood circuit. |
| 17 | DRVL | output | Rectifying (low-side) MOSFET gate-drive output. |
| 18 | LL | bidirectional | High-side MOSFET gate driver return and current sense comparator input (-) for RDS(on) current sensing. |
| 19 | DRVH | output | Switching (high-side) MOSFET gate-drive output. |
| 20 | VBST | bidirectional | Switching (high-side) MOSFET driver bootstrap voltage input. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range, VBST | VBST | -0.3 | 36 | V | 4 | ||
| VBST wrt LL | VBST wrt LL | -0.3 | 6 | V | 4 | ||
| Voltage range, CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET, V5FILT | -0.3 | 6 | V | 4 | |||
| Voltage range, PGND, VTTGND, CS_GND | -0.3 | 0.3 | V | 4 | |||
| Output voltage range, DRVH | DRVH | -1 | 36 | V | 4 | ||
| Output voltage range, LL | LL | -1 | 30 | V | 4 | ||
| Output voltage range, COMP, DRVL, PGOOD, VTT, VTTREF | -0.3 | 6 | V | 4 | |||
| Operating ambient temperature range | TA | -40 | 85 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Supply voltage, V5IN, V5FILT | 4.75 | 5.25 | V | 4 | |||
| Voltage range, VBST, DRVH | -0.1 | 34 | V | 4 | |||
| Voltage range, LL | LL | -0.6 | 28 | V | 4 | ||
| Voltage range, VLDOIN, VTT, VTTSNS, VDDQSNS | -0.1 | 3.6 | V | 4 | |||
| Voltage range, VTTREF | VTTREF | -0.1 | 1.8 | V | 4 | ||
| Voltage range, PGND, VTTGND, CS_GND | -0.1 | 0.1 | V | 4 | |||
| Voltage range, S3, S5, MODE, VDDQSET, CS, COMP, PGOOD, DRVL | -0.1 | 5.25 | V | 4 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| Supply current 1, V5IN | IV5IN1 | 0.8 | 2 | mA | TA = 25°C, No load, VS3 = VS5 = 5 V, COMP connected to capacitor | 5 | |
| Supply current 2, V5IN | IV5IN2 | 300 | 600 | μA | TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, COMP connected to capacitor | 5 | |
| Supply current 3, V5IN | IV5IN3 | 240 | 500 | μA | TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VCOMP = 5 V | 5 | |
| Shutdown current, V5IN | IV5INSDN | 0.1 | 1 | μA | TA = 25°C, No load, VS3 = VS5 = 0 V | 5 | |
| Supply current 1, VLDOIN | IVLDOIN1 | 1 | 10 | μA | TA = 25°C, No load, VS3 = VS5 = 5 V | 5 | |
| VTTREF output voltage tolerance, VDDQSNS = 2.5 V | VVTTREFTOL | -20 | 20 | mV | -10 mA < IVTTREF < 10 mA, VVDDQSNS = 2.5 V, tolerance to VVDDQSNS/2 | 5 | |
| VTTREF output voltage tolerance, VDDQSNS = 1.8 V | VVTTREFTOL | -18 | 18 | mV | -10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.8 V, tolerance to VVDDQSNS/2 | 5 | |
| VTTREF output voltage tolerance, VDDQSNS = 1.5 V | VVTTREFTOL | -15 | 15 | mV | -10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.5 V, tolerance to VVDDQSNS/2 | 5 | |
| VTTREF output voltage tolerance, VDDQSNS = 1.2 V | VVTTREFTOL | -12 | 12 | mV | -10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.2 V, tolerance to VVDDQSNS/2 | 5 | |
| Source current | VVTTREFSRC | -20 | -40 | -80 | mA | VVDDQSNS = 2.5 V, VVTTREF = 0 V | 5 |
| Sink current | VVTTREFSNK | 20 | 40 | 80 | mA | VVDDQSNS = 2.5 V, VVTTREF = 2.5 V | 5 |
| Output voltage, VDDQ | VVDDQ | 2.465 | 2.5 | 2.535 | V | TA = 25°C, VVDDQSET = 0 V, No load | 6 |
| Output voltage, VDDQ | VVDDQ | 2.457 | 2.5 | 2.543 | V | 0°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load | 6 |
| Output voltage, VDDQ | VVDDQ | 2.44 | 2.5 | 2.55 | V | -40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load | 6 |
| Output voltage, VDDQ | VVDDQ | 1.776 | 1.8 | 1.824 | V | TA = 25°C, VVDDQSET = 5 V, No load | 6 |
| Output voltage, VDDQ | VVDDQ | 1.769 | 1.8 | 1.831 | V | 0°C ≤ TA ≤ 85°C, VVDDQSET = 5 V, No load | 6 |
| Output voltage, VDDQ | VVDDQ | 1.764 | 1.8 | 1.836 | V | -40°C ≤ TA ≤ 85°C, VVDDQSET = 5 V, No load | 6 |
| Output voltage, VDDQ adjustable range | VVDDQ | 0.75 | 3 | V | -40°C ≤ TA ≤ 85°C, Adjustable mode, No load | 6 | |
| VTT output voltage tolerance to VTTREF | VVTTTOL25 | -20 | 20 | mV | VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, IVTT = 0 A | 6 | |
| VTT output voltage tolerance to VTTREF | VVTTTOL25 | -30 | 30 | mV | VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, /IVTT/ < 1.5 A | 6 | |
| VTT output voltage tolerance to VTTREF | VVTTTOL25 | -40 | 40 | mV | VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, /IVTT/ < 3 A | 6 | |
| Source current limit, VTT | IVTTOCLSRC | 3 | 3.8 | 6 | A | VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.19 V, PGOOD = HI | 7 |
| Source current limit, VTT | IVTTOCLSRC | 1.5 | 2.2 | 3 | A | VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V | 7 |
| Sink current limit, VTT | IVTTOCLSNK | 3 | 3.6 | 6 | A | VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.31 V, PGOOD = HI | 7 |
| Sink current limit, VTT | IVTTOCLSNK | 1.5 | 2.2 | 3 | A | VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ | 7 |
| Gain | gm | 240 | 300 | 360 | μS | TA = 25°C | 7 |
| COMP high clamp voltage | VCOMPHI | 1.31 | 1.34 | 1.37 | V | VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCS = 0 V | 7 |
| COMP low clamp voltage | VCOMPLO | 1.18 | 1.21 | 1.24 | V | VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCS = 0 V | 7 |
| Zero current comparator offset | VZC | -6 | 0 | 6 | mV | 7 | |
| Forward voltage | VFBST | 0.7 | 0.8 | 0.9 | V | VV5IN-VBST, IF = 10 mA, TA = 25°C | 7 |
| VBST leakage current | IVBSTLK | 0.1 | 1 | μA | VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V, TA = 25°C | 7 | |
| Junction-to-ambient thermal resistance, PWP | RθJA | 41.2 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance, PWP | RθJC(top) | 27.4 | °C/W | 5 | |||
| Junction-to-board thermal resistance, PWP | RθJB | 23.9 | °C/W | 5 | |||
| Junction-to-top characterization parameter, PWP | ψJT | 1.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter, PWP | ψJB | 23.7 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance, PWP | RθJC(bot) | 3.6 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS51116PWP - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files:
tps51116pwp-etched.step/tps51116pwp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps51116pwp.step/tps51116pwp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
2bcc993ec5d308e1, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).