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TPS43061RTET

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Texas Instruments DC-DC Converters, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS43061RTET

Texas Instruments · DC-DC Converters · WQFN-16-EP(3x3)

TPS43061RTET from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RT/CLK input Resistor timing and external clock pin: a resistor to AGND programs switching frequency between 50 kHz and 1 MHz, or an external clock of 300 kHz to 1 MHz synchronizes it.
2 SS passive Soft-start programming pin; a capacitor between SS and AGND sets the soft-start time.
3 COMP output Output of the internal transconductance error amplifier; the loop compensation network connects from this pin to AGND.
4 FB input Error amplifier input and feedback pin; connect to the center tap of a resistor divider to set the output voltage (reference 1.22 V typical).
5 ISNS- input Inductor current sense comparator inverting input, normally connected to the inductor side of the current sense resistor.
6 ISNS+ input Inductor current sense comparator non-inverting input, normally connected to the VIN side of the current sense resistor.
7 VIN power_in Input supply pin of the IC, connected to a supply voltage between 4.5 and 38 V, which may differ from the boost power stage input.
8 LDRV output Low-side gate driver output to the gate of the low-side N-channel MOSFET; an internal 200-kΩ resistor pulls it to PGND when VIN bias is removed.
9 PGND power_in Power ground of the IC, connected to the source of the low-side MOSFET and tied to AGND at a single point on the PCB.
10 VCC power_out Output of the internal LDO supplying control circuits and gate drivers, typically 5.5 V for the TPS43061; use a low-ESR ceramic capacitor of 0.47 to 10 µF to PGND.
11 BOOT passive Bootstrap capacitor node for the high-side MOSFET gate driver; connect the bootstrap capacitor from this pin to SW (the TPS43061 has an integrated bootstrap diode).
12 SW passive Switching node of the boost converter, connected to the low-side MOSFET drain, high-side synchronous MOSFET source and the inductor.
13 HDRV output High-side gate driver output to the gate of the synchronous rectifier MOSFET; connected to SW through an internal 200-kΩ resistor when VIN bias is removed.
14 PGOOD output Open-drain power good indicator; a 10-kΩ pullup to VCC or an external logic supply is recommended.
15 EN input Enable pin with internal pullup current source; floating enables the IC, below 1.2 V enters standby, below 0.4 V enters shutdown, and two resistors can set adjustable UVLO.
16 AGND power_in Analog signal ground of the IC, connected to PGND at a single point on the PCB.
17 PowerPAD power_in Exposed PowerPAD connected to AGND, with thermal vias to an internal ground plane if possible for improved power dissipation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-16-EP(3x3)
Category Power Supply Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN -0.3 40 V VIN, EN, ISNS+, ISNS- 4
SW DC voltage SW -0.6 60 V DC 4
SW transient voltage SW -2 60 V 10 ns max 4
FB, RT/CLK, COMP, SS voltage -0.3 3.6 V 4
BOOT, HDRV voltage wrt ground 65 V with respect to ground 4
BOOT, HDRV voltage wrt SW 8 V with respect to SW pin 4
VCC, PGOOD, LDRV voltage -0.3 8 V 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature range Tstg -65 150 °C 4
ESD HBM V(ESD) -2000 2000 V Human body model, all pins 4
ESD CDM V(ESD) -500 500 V Charged device model, all pins 4
Input voltage range VIN 4.5 38 V 4
Output voltage range VOUT 58 V min is VIN 4
EN voltage range VEN 0 38 V 4
External switching frequency logic input range VCLK 0 3.6 V 4
Operating junction temperature TJ -40 150 °C 4
Junction-to-ambient thermal resistance RθJA 65.7 °C/W WQFN 16-pin 4
Junction-to-case (top) thermal resistance RθJC(top) 42.3 °C/W 4
Junction-to-board thermal resistance RθJB 18 °C/W 4
Junction-to-case (bottom) thermal resistance RθJC(bot) 22.7 °C/W 4
Input voltage range VIN 4.5 38 V 5
Input undervoltage threshold, falling VUV 3.7 3.9 4 V VIN falling 5
Input undervoltage threshold, rising VUV 3.9 4.1 4.3 V VIN rising 5
Operating quiescent current into VIN IQ 600 800 µA Device non-switching, RT = 115 kΩ, VFB = 2 V 5
Shutdown current ISD 1.5 5 µA VEN = 0.4 V 5
EN threshold to standby VEN 0.4 0.7 0.9 V VEN ramping down 5
EN threshold to enable VEN 1.12 1.21 1.29 V VEN ramping up 5
EN threshold to disable VEN 1 1.14 1.28 V VEN ramping down 5
EN hysteresis current IEN 3.2 4.6 µA VEN = 1.3 V 5
Feedback voltage reference VREF 1.21 1.22 1.23 V TJ = 25°C 5
Feedback voltage reference VREF 1.195 1.22 1.244 V TJ = -40°C to 150°C 5
Maximum current sense threshold VCSmax 64 73 82 mV At 0% duty cycle 5
Maximum current sense threshold VCSmax 50 61 72 mV At max duty cycle 5
Switching frequency range ƒSW 50 1000 kHz Operating frequency range using resistor timing mode 5
Switching frequency ƒSW 450 500 550 kHz RT = 115 kΩ 5
Switching frequency ƒSW 675 750 825 kHz RT = 75 kΩ 5
Minimum input clock pulse duration tCLK-min 14 60 ns PLL = 500 kHz 5
RT/CLK high threshold vCLK-H 1.78 2 V 6
RT/CLK low threshold ƒCLK 0.4 1.35 V 6
PLL frequency sync range ƒCLK 300 1000 kHz 6
PLL lock in time tPLLIN 100 250 µs 6
Last RT/CLK falling edge to resistor timing mode return tPLLEXIT 140 250 µs if CLK is not present 6
PGOOD low threshold PGDL 86 90 93 % VFB with respect to feedback voltage reference, VFB falling 7
PGOOD high threshold PGDH 107 110 114 % VFB with respect to feedback voltage reference, VFB rising 7
PGOOD sink current PGDSC 1.8 4 mA VPGOOD = 0.4 V 7
Minimum VIN for valid PGOOD VIN_PGD 2.5 4.3 V 7
OVP threshold VOVP 104 107 110 % VFB with respect to feedback voltage reference, VFB rising 7
PGOOD pin leakage current PGDLK 100 nA VPGOOD = 7 V 7
Thermal shutdown set threshold TSD 165 °C 7
Thermal shutdown hysteresis Thyst 15 °C 7

CAD (KiCad official)

  • Symbol: TPS43061RTET
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps43061rtet-etched.step / tps43061rtet-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps43061rtet.step / tps43061rtet.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 2cd9f6a548135d9e, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF