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TPS40428RHAR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS40428RHAR
Texas Instruments · AC-DC Controllers And Regulators · VQFN-40-EP(6x6)
TPS40428RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | bidirectional | Synchronization pin for an external clock; the external SYNC frequency must be 4 times the desired switching frequency in 1-, 2-, or 4-phase operation and 3 times in 3-phase operation. |
| 2 | PHSET | bidirectional | Phase set pin for multiphase mode, tied to the PHSET bus in 3- and 4-phase configurations to set the phase shift between devices. |
| 3 | CNTL1 | input | Logic-level input that starts or stops channel 1; an internal 6-µA current source pulls it up to VBP5 when the pin is floating. |
| 4 | CNTL2 | input | Logic-level input that starts or stops channel 2; an internal 6-µA current source pulls it up to VBP5 when the pin is floating. |
| 5 | SMBALERT | output | PMBus alert pin for the SMBALERT response protocol; pull up to BP3 via a 100 kΩ resistor when unused. |
| 6 | PMBDATA | bidirectional | PMBus data pin; pull up to BP3 via a 100 kΩ resistor when unused. |
| 7 | PMBCLK | input | PMBus clock pin supporting both 100-kHz and 400-kHz bus speeds; pull up to BP3 via a 100 kΩ resistor when unused. |
| 8 | AGND | power_in | Analog ground pin for analog signals; connect directly to the thermal pad. |
| 9 | AVSDATA | input | AVS data line for the high-speed AVSBUS; must connect to the AVS host when the AVS interface is used, and may float or connect to GND if AVS mode is disabled. |
| 10 | AVSCLK | input | AVS clock line for the high-speed AVSBUS; must connect to the AVS host when the AVS interface is used, and may float or connect to GND if AVS mode is disabled. |
| 11 | ADDR1 | input | High-order digit pin of the PMBus address; connect a resistor to AGND as given in Table 3. |
| 12 | ADDR0 | input | Low-order digit pin of the PMBus address; connect a resistor to AGND as given in Table 3. |
| 13 | GSNS2 | input | Negative pin of the voltage sense signal for channel 2; connect to GND (connection to the output voltage is also allowed in dual-output mode). |
| 14 | VSNS2 | input | Positive pin of the voltage sense signal for channel 2. |
| 15 | COMP2 | output | Output of error amplifier 2 and connection node for the loop feedback components. |
| 16 | FB2 | input | Inverting input to error amplifier 2, which in normal operation equals the internal 0.6 V reference; connect to BP5 to set the channel as a slave. |
| 17 | FLT2 | bidirectional | Fault signal of channel 2, pulled to BP3 through an internal 100 kΩ resistor. |
| 18 | CS2N | input | Negative pin of the channel 2 current sense amplifier; an internal 4 kΩ resistor pulls it to 1.24 V in smart power mode to bias the smart power stage. |
| 19 | CS2P | input | Positive pin of the channel 2 current sense amplifier. |
| 20 | TSNS2 | input | External temperature sense signal input for channel 2. |
| 21 | ISH2 | input | Current sharing signal of channel 2 for multiphase mode; tie to the ISH bus. |
| 22 | PG2 | output | Open-drain power good indicator for the channel 2 output voltage; pulled to ground internally in slave channel. |
| 23 | PWM2 | output | PWM signal output for channel 2. |
| 24 | VDD | power_in | Power input to the controller with an input operating voltage of 4.5 V to 20 V; connect a low-ESR ceramic capacitor of 1 µF or greater closely from this pin to AGND. |
| 25 | BP5 | power_out | Output bypass for the internal regulator; connect a low-ESR ceramic capacitor of 1 µF or greater closely from this pin to PGND, with a maximum suggested value of 10 µF. |
| 26 | BP3 | power_out | 3.3-V bias power for logic; connect a low-ESR ceramic capacitor of 0.33 µF or greater closely from this pin to AGND, with a maximum suggested value of 10 µF. |
| 27 | PGND | power_in | Power ground used for the BP5 bypass capacitor; connect directly to the thermal pad. |
| 28 | PWM1 | output | PWM signal output for channel 1. |
| 29 | PG1 | output | Open-drain power good indicator for the channel 1 output voltage; pulled to ground internally in slave channel. |
| 30 | ISH1 | input | Current sharing signal of channel 1 for multiphase mode; tie to the ISH bus. |
| 31 | TSNS1 | input | External temperature sense signal input for channel 1. |
| 32 | CS1P | input | Positive pin of the channel 1 current sense amplifier. |
| 33 | CS1N | input | Negative pin of the channel 1 current sense amplifier; an internal 4 kΩ resistor pulls it to 1.24 V in smart power mode to bias the smart power stage. |
| 34 | FLT1 | bidirectional | Fault signal of channel 1, pulled to BP3 through an internal 100 kΩ resistor. |
| 35 | FB1 | input | Inverting input to error amplifier 1, which in normal operation equals the internal 0.6 V reference; connect to BP5 to set the channel as a slave. |
| 36 | COMP1 | output | Output of error amplifier 1 and connection node for the loop feedback components. |
| 37 | VSNS1 | input | Positive pin of the voltage sense signal for channel 1. |
| 38 | GSNS1 | input | Negative pin of the voltage sense signal for channel 1. |
| 39 | DIFFO1 | output | Remote sense amplifier output for channel 1. |
| 40 | RT | input | Connect a resistor from this pin to AGND to set the oscillator frequency. |
| 41 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
TPS40428RHAR - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
tps40428rhar-etched.step/tps40428rhar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps40428rhar.step/tps40428rhar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (93 pp, sha256
21c3662a008c761c, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS40428RHAR
**Texas Instruments** · AC-DC Controllers And Regulators · VQFN-40-EP(6x6)
TPS40428RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | bidirectional | Synchronization pin for an external clock; the external SYNC frequency must be 4 times the desired switching frequency in 1-, 2-, or 4-phase operation and 3 times in 3-phase operation. |
| 2 | PHSET | bidirectional | Phase set pin for multiphase mode, tied to the PHSET bus in 3- and 4-phase configurations to set the phase shift between devices. |
| 3 | CNTL1 | input | Logic-level input that starts or stops channel 1; an internal 6-µA current source pulls it up to VBP5 when the pin is floating. |
| 4 | CNTL2 | input | Logic-level input that starts or stops channel 2; an internal 6-µA current source pulls it up to VBP5 when the pin is floating. |
| 5 | SMBALERT | output | PMBus alert pin for the SMBALERT response protocol; pull up to BP3 via a 100 kΩ resistor when unused. |
| 6 | PMBDATA | bidirectional | PMBus data pin; pull up to BP3 via a 100 kΩ resistor when unused. |
| 7 | PMBCLK | input | PMBus clock pin supporting both 100-kHz and 400-kHz bus speeds; pull up to BP3 via a 100 kΩ resistor when unused. |
| 8 | AGND | power_in | Analog ground pin for analog signals; connect directly to the thermal pad. |
| 9 | AVSDATA | input | AVS data line for the high-speed AVSBUS; must connect to the AVS host when the AVS interface is used, and may float or connect to GND if AVS mode is disabled. |
| 10 | AVSCLK | input | AVS clock line for the high-speed AVSBUS; must connect to the AVS host when the AVS interface is used, and may float or connect to GND if AVS mode is disabled. |
| 11 | ADDR1 | input | High-order digit pin of the PMBus address; connect a resistor to AGND as given in Table 3. |
| 12 | ADDR0 | input | Low-order digit pin of the PMBus address; connect a resistor to AGND as given in Table 3. |
| 13 | GSNS2 | input | Negative pin of the voltage sense signal for channel 2; connect to GND (connection to the output voltage is also allowed in dual-output mode). |
| 14 | VSNS2 | input | Positive pin of the voltage sense signal for channel 2. |
| 15 | COMP2 | output | Output of error amplifier 2 and connection node for the loop feedback components. |
| 16 | FB2 | input | Inverting input to error amplifier 2, which in normal operation equals the internal 0.6 V reference; connect to BP5 to set the channel as a slave. |
| 17 | FLT2 | bidirectional | Fault signal of channel 2, pulled to BP3 through an internal 100 kΩ resistor. |
| 18 | CS2N | input | Negative pin of the channel 2 current sense amplifier; an internal 4 kΩ resistor pulls it to 1.24 V in smart power mode to bias the smart power stage. |
| 19 | CS2P | input | Positive pin of the channel 2 current sense amplifier. |
| 20 | TSNS2 | input | External temperature sense signal input for channel 2. |
| 21 | ISH2 | input | Current sharing signal of channel 2 for multiphase mode; tie to the ISH bus. |
| 22 | PG2 | output | Open-drain power good indicator for the channel 2 output voltage; pulled to ground internally in slave channel. |
| 23 | PWM2 | output | PWM signal output for channel 2. |
| 24 | VDD | power_in | Power input to the controller with an input operating voltage of 4.5 V to 20 V; connect a low-ESR ceramic capacitor of 1 µF or greater closely from this pin to AGND. |
| 25 | BP5 | power_out | Output bypass for the internal regulator; connect a low-ESR ceramic capacitor of 1 µF or greater closely from this pin to PGND, with a maximum suggested value of 10 µF. |
| 26 | BP3 | power_out | 3.3-V bias power for logic; connect a low-ESR ceramic capacitor of 0.33 µF or greater closely from this pin to AGND, with a maximum suggested value of 10 µF. |
| 27 | PGND | power_in | Power ground used for the BP5 bypass capacitor; connect directly to the thermal pad. |
| 28 | PWM1 | output | PWM signal output for channel 1. |
| 29 | PG1 | output | Open-drain power good indicator for the channel 1 output voltage; pulled to ground internally in slave channel. |
| 30 | ISH1 | input | Current sharing signal of channel 1 for multiphase mode; tie to the ISH bus. |
| 31 | TSNS1 | input | External temperature sense signal input for channel 1. |
| 32 | CS1P | input | Positive pin of the channel 1 current sense amplifier. |
| 33 | CS1N | input | Negative pin of the channel 1 current sense amplifier; an internal 4 kΩ resistor pulls it to 1.24 V in smart power mode to bias the smart power stage. |
| 34 | FLT1 | bidirectional | Fault signal of channel 1, pulled to BP3 through an internal 100 kΩ resistor. |
| 35 | FB1 | input | Inverting input to error amplifier 1, which in normal operation equals the internal 0.6 V reference; connect to BP5 to set the channel as a slave. |
| 36 | COMP1 | output | Output of error amplifier 1 and connection node for the loop feedback components. |
| 37 | VSNS1 | input | Positive pin of the voltage sense signal for channel 1. |
| 38 | GSNS1 | input | Negative pin of the voltage sense signal for channel 1. |
| 39 | DIFFO1 | output | Remote sense amplifier output for channel 1. |
| 40 | RT | input | Connect a resistor from this pin to AGND to set the oscillator frequency. |
| 41 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 41 |
## CAD (KiCad official)
- Symbol: `TPS40428RHAR`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `tps40428rhar-etched.step` / `tps40428rhar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps40428rhar.step` / `tps40428rhar.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps40428) (93 pp, sha256 `21c3662a008c761c`, retrieved 2026-10-10, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps40428rhar-datasheet.pdf)