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TPS40422RHAT
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Texas Instruments DC-DC Converters, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS40422RHAT
Texas Instruments · DC-DC Converters · VQFN-40-EP(6x6)
TPS40422RHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RT | input | Frequency programming pin; connect a resistor from RT to AGND to set the oscillator frequency within the 200 kHz to 1 MHz programmable range. |
| 2 | FB1 | input | Inverting input of the CH1 error amplifier; a voltage divider from DIFFO1 to AGND programs the CH1 output voltage. |
| 3 | COMP1 | output | Output of the CH1 error amplifier and connection node for loop feedback components; for two-phase operation it is connected to COMP2. |
| 4 | CNTL1 | input | Logic-level input controlling CH1 startup and shutdown per PMBus options; when floating it is pulled up to BP6 by an internal 6-µA current source. |
| 5 | CNTL2 | input | Logic-level input controlling CH2 startup and shutdown per PMBus options; when floating it is pulled up to BP6 by an internal 6-µA current source. |
| 6 | AGND | power_in | Low-noise ground connection to the controller, arranged so that power-level currents do not flow through the AGND path. |
| 7 | COMP2 | output | Output of the CH2 error amplifier and connection node for loop feedback components; for two-phase operation it is connected to COMP1. |
| 8 | FB2 | input | Inverting input of the CH2 error amplifier; a divider between VOUT2 and GND programs the CH2 output, and in two-phase operation FB2 is connected to BP6 before VDD is applied. |
| 9 | ADDR1 | input | High-order PMBus address pin; one of eight resistor values connected from this pin to AGND selects the high-order octal digit of the address. |
| 10 | ADDR0 | input | Low-order PMBus address pin; one of eight resistor values connected from this pin to AGND selects the low-order octal digit of the address. |
| 11 | DATA | bidirectional | Data input/output for the PMBus interface, which must be pulled up to 3.3 V with a resistor. |
| 12 | CLK | input | Clock input for the PMBus interface, which must be pulled up to 3.3 V with a resistor. |
| 13 | SMBALRT | output | Alert output for the PMBus interface, which must be pulled up to 3.3 V with a resistor. |
| 14 | GSNS2 | input | Negative terminal of the CH2 differential remote sense amplifier. |
| 15 | VSNS2 | input | Positive terminal of the CH2 differential remote sense amplifier. |
| 16 | TSNS2 | input | External temperature sense input for CH2. |
| 17 | CS2N | input | Negative terminal of the CH2 current sense amplifier. |
| 18 | CS2P | input | Positive terminal of the CH2 current sense amplifier. |
| 19 | PG2 | output | Open-drain power-good indicator for the CH2 output voltage. |
| 20 | BOOT2 | power_in | Bootstrapped supply for the CH2 high-side FET driver; connect a 100 nF typical capacitor from BOOT2 to SW2. |
| 21 | HDRV2 | output | Bootstrapped gate drive output for the CH2 high-side N-channel MOSFET. |
| 22 | SW2 | input | Return of the CH2 high-side gate driver, connected to the CH2 switched node. |
| 23 | LDRV2 | output | Gate drive output for the CH2 low-side synchronous rectifier N-channel MOSFET. |
| 24 | BPEXT | input | External voltage input for the BP6 switchover function; if unused, connect to PGND through 10 kΩ, otherwise use a 100 nF or larger capacitor to PGND with a maximum suggested value of 10 µF. |
| 25 | BP6 | power_out | Output bypass for the internal 6.5-V regulator; connect a low-ESR ceramic capacitor of 1 µF or larger from BP6 to PGND, with a maximum suggested value of 10 µF. |
| 26 | PGND | power_in | Power ground for the device. |
| 27 | LDRV1 | output | Gate drive output for the CH1 low-side synchronous rectifier N-channel MOSFET. |
| 28 | SW1 | input | Return of the CH1 high-side gate driver, connected to the CH1 switched node. |
| 29 | HDRV1 | output | Bootstrapped gate drive output for the CH1 high-side N-channel MOSFET. |
| 30 | BOOT1 | power_in | Bootstrapped supply for the CH1 high-side FET driver; connect a 100 nF typical capacitor from BOOT1 to SW1. |
| 31 | VDD | power_in | Power input to the controller, operating from 4.5 V to 20 V; connect a low-ESR ceramic capacitor of 100 nF or larger from VDD to AGND. |
| 32 | BP3 | power_out | Output bypass for the internal 3.3-V regulator; connect a 100 nF or larger capacitor from BP3 to AGND, with a maximum suggested value of 10 µF. |
| 33 | PG1 | output | Open-drain power-good indicator for the CH1 output voltage. |
| 34 | CS1P | input | Positive terminal of the CH1 current sense amplifier. |
| 35 | CS1N | input | Negative terminal of the CH1 current sense amplifier. |
| 36 | TSNS1 | input | External temperature sense input for CH1. |
| 37 | VSNS1 | input | Positive terminal of the CH1 differential remote sense amplifier. |
| 38 | GSNS1 | input | Negative terminal of the CH1 differential remote sense amplifier. |
| 39 | DIFFO1 | output | Output of the CH1 differential remote sense amplifier, which feeds the CH1 feedback divider. |
| 40 | SYNC | input | Logic-level external clock synchronization input; the switching frequency becomes one half of the external clock frequency, and it must be tied to AGND when no external clock is used. |
| 41 | PWPD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
TPS40422RHAT - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
tps40422rhat-etched.step/tps40422rhat-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps40422rhat.step/tps40422rhat.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (77 pp, sha256
5149865e86388b29, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS40422RHAT
**Texas Instruments** · DC-DC Converters · VQFN-40-EP(6x6)
TPS40422RHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RT | input | Frequency programming pin; connect a resistor from RT to AGND to set the oscillator frequency within the 200 kHz to 1 MHz programmable range. |
| 2 | FB1 | input | Inverting input of the CH1 error amplifier; a voltage divider from DIFFO1 to AGND programs the CH1 output voltage. |
| 3 | COMP1 | output | Output of the CH1 error amplifier and connection node for loop feedback components; for two-phase operation it is connected to COMP2. |
| 4 | CNTL1 | input | Logic-level input controlling CH1 startup and shutdown per PMBus options; when floating it is pulled up to BP6 by an internal 6-µA current source. |
| 5 | CNTL2 | input | Logic-level input controlling CH2 startup and shutdown per PMBus options; when floating it is pulled up to BP6 by an internal 6-µA current source. |
| 6 | AGND | power_in | Low-noise ground connection to the controller, arranged so that power-level currents do not flow through the AGND path. |
| 7 | COMP2 | output | Output of the CH2 error amplifier and connection node for loop feedback components; for two-phase operation it is connected to COMP1. |
| 8 | FB2 | input | Inverting input of the CH2 error amplifier; a divider between VOUT2 and GND programs the CH2 output, and in two-phase operation FB2 is connected to BP6 before VDD is applied. |
| 9 | ADDR1 | input | High-order PMBus address pin; one of eight resistor values connected from this pin to AGND selects the high-order octal digit of the address. |
| 10 | ADDR0 | input | Low-order PMBus address pin; one of eight resistor values connected from this pin to AGND selects the low-order octal digit of the address. |
| 11 | DATA | bidirectional | Data input/output for the PMBus interface, which must be pulled up to 3.3 V with a resistor. |
| 12 | CLK | input | Clock input for the PMBus interface, which must be pulled up to 3.3 V with a resistor. |
| 13 | SMBALRT | output | Alert output for the PMBus interface, which must be pulled up to 3.3 V with a resistor. |
| 14 | GSNS2 | input | Negative terminal of the CH2 differential remote sense amplifier. |
| 15 | VSNS2 | input | Positive terminal of the CH2 differential remote sense amplifier. |
| 16 | TSNS2 | input | External temperature sense input for CH2. |
| 17 | CS2N | input | Negative terminal of the CH2 current sense amplifier. |
| 18 | CS2P | input | Positive terminal of the CH2 current sense amplifier. |
| 19 | PG2 | output | Open-drain power-good indicator for the CH2 output voltage. |
| 20 | BOOT2 | power_in | Bootstrapped supply for the CH2 high-side FET driver; connect a 100 nF typical capacitor from BOOT2 to SW2. |
| 21 | HDRV2 | output | Bootstrapped gate drive output for the CH2 high-side N-channel MOSFET. |
| 22 | SW2 | input | Return of the CH2 high-side gate driver, connected to the CH2 switched node. |
| 23 | LDRV2 | output | Gate drive output for the CH2 low-side synchronous rectifier N-channel MOSFET. |
| 24 | BPEXT | input | External voltage input for the BP6 switchover function; if unused, connect to PGND through 10 kΩ, otherwise use a 100 nF or larger capacitor to PGND with a maximum suggested value of 10 µF. |
| 25 | BP6 | power_out | Output bypass for the internal 6.5-V regulator; connect a low-ESR ceramic capacitor of 1 µF or larger from BP6 to PGND, with a maximum suggested value of 10 µF. |
| 26 | PGND | power_in | Power ground for the device. |
| 27 | LDRV1 | output | Gate drive output for the CH1 low-side synchronous rectifier N-channel MOSFET. |
| 28 | SW1 | input | Return of the CH1 high-side gate driver, connected to the CH1 switched node. |
| 29 | HDRV1 | output | Bootstrapped gate drive output for the CH1 high-side N-channel MOSFET. |
| 30 | BOOT1 | power_in | Bootstrapped supply for the CH1 high-side FET driver; connect a 100 nF typical capacitor from BOOT1 to SW1. |
| 31 | VDD | power_in | Power input to the controller, operating from 4.5 V to 20 V; connect a low-ESR ceramic capacitor of 100 nF or larger from VDD to AGND. |
| 32 | BP3 | power_out | Output bypass for the internal 3.3-V regulator; connect a 100 nF or larger capacitor from BP3 to AGND, with a maximum suggested value of 10 µF. |
| 33 | PG1 | output | Open-drain power-good indicator for the CH1 output voltage. |
| 34 | CS1P | input | Positive terminal of the CH1 current sense amplifier. |
| 35 | CS1N | input | Negative terminal of the CH1 current sense amplifier. |
| 36 | TSNS1 | input | External temperature sense input for CH1. |
| 37 | VSNS1 | input | Positive terminal of the CH1 differential remote sense amplifier. |
| 38 | GSNS1 | input | Negative terminal of the CH1 differential remote sense amplifier. |
| 39 | DIFFO1 | output | Output of the CH1 differential remote sense amplifier, which feeds the CH1 feedback divider. |
| 40 | SYNC | input | Logic-level external clock synchronization input; the switching frequency becomes one half of the external clock frequency, and it must be tied to AGND when no external clock is used. |
| 41 | PWPD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 41 |
## CAD (KiCad official)
- Symbol: `TPS40422RHAT`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `tps40422rhat-etched.step` / `tps40422rhat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps40422rhat.step` / `tps40422rhat.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps40422) (77 pp, sha256 `5149865e86388b29`, retrieved 2026-10-10, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps40422rhat-datasheet.pdf)