component
TPS40322RHBR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+69@@ -0,0 +1,69 @@+# TPS40322RHBR++**Texas Instruments** · DC-DC Converters · VQFN-32-EP(5x5)++TPS40322RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SYNC | bidirectional | Bidirectional synchronization pin; outputs 2x free running clock in master mode or syncs to external clock (±20% range) in slave mode with 50% duty cycle, must be left floating when unused. |+| 2 | RT | input | Connect resistor from this pin to AGND to set oscillator frequency from 100 kHz to 1 MHz. |+| 3 | EN1/SS1 | input | Logic level enable input for CH1 (float=on, low=off); soft-start programming pin charged by internal 10 μA current source. |+| 4 | FB1 | input | Inverting input to error amplifier CH1; voltage equals internal 0.600 V reference under normal operation. |+| 5 | COMP1 | output | Output of error amplifier 1 and connection node for loop compensation network components. |+| 6 | AGND | power_in | Low noise analog ground connection to controller. |+| 7 | COMP2 | output | Output of error amplifier 2 and connection node for loop compensation network components. |+| 8 | FB2 | input | Inverting input to error amplifier CH2; voltage equals internal 0.600 V reference; connecting to BP6 enables two-phase mode. |+| 9 | DIFFO | output | Differential amplifier output; must float or tie to BP6 in dual-channel mode. |+| 10 | EN2/SS2/GSNS | input | Logic level enable input for CH2 (float=on, low=off) with 10 μA soft-start charging current; functions as GSNS (negative sense terminal) in two-phase mode. |+| 11 | ILIM2/VSNS | input | Set CH2 overcurrent limit using 10 μA from this pin to AGND; functions as VSNS (positive sense terminal) in two-phase mode. |+| 12 | CS2- | input | Negative terminal of current sense amplifier for CH2; typical voltage drop < 50 mV. |+| 13 | CS2+ | input | Positive terminal of current sense amplifier for CH2; typical voltage drop < 50 mV. |+| 14 | PG2 | output | Open-drain power good indicator for CH2; pulls low if output ±12.5% from nominal or soft-start active. |+| 15 | BOOT2 | power_out | Bootstrap supply for high-side FET driver CH2; connect 0.1 μF capacitor from BOOT2 to SW2 with ripple <100 mV. |+| 16 | HDRV2 | output | Bootstrapped gate drive output for high-side N-channel MOSFET CH2; 2 Ω series resistor recommended in noisy environments. |+| 17 | SW2 | input | Connect to switched node voltage of CH2 converter; provides return path for high-side gate driver HDRV2. |+| 18 | LDRV2 | output | Gate drive output for low-side synchronous rectifier N-channel MOSFET CH2. |+| 19 | PGND2 | power_in | Power ground connection for CH2; separate PCB layout from PGND1 reduces channel-to-channel interference. |+| 20 | BP6 | power_out | Internal regulator 3.3 V bypass output; connect 3.3 μF minimum low-ESR ceramic capacitor to power ground plane. |+| 21 | PGND1 | power_in | Power ground connection for CH1; separate PCB layout from PGND2 reduces channel-to-channel interference. |+| 22 | LDRV1 | output | Gate drive output for low-side synchronous rectifier N-channel MOSFET CH1. |+| 23 | SW1 | input | Connect to switched node voltage of CH1 converter; provides return path for high-side gate driver HDRV1. |+| 24 | HDRV1 | output | Bootstrapped gate drive output for high-side N-channel MOSFET CH1; 2 Ω series resistor recommended in noisy environments. |+| 25 | BOOT1 | power_out | Bootstrap supply for high-side FET driver CH1; connect 0.1 μF capacitor from BOOT1 to SW1 with ripple <100 mV. |+| 26 | VDD | power_in | Power supply input (3 V to 20 V); connect 0.1 μF minimum low-ESR bypass capacitor closely to AGND. |+| 27 | PG1 | output | Open-drain power good indicator for CH1; pulls low if output ±12.5% from nominal or soft-start active. |+| 28 | CS1+ | input | Positive terminal of current sense amplifier for CH1; typical voltage drop < 50 mV. |+| 29 | CS1- | input | Negative terminal of current sense amplifier for CH1; typical voltage drop < 50 mV. |+| 30 | ILIM1 | input | Set CH1 overcurrent limit using 10 μA from this pin to AGND. |+| 31 | UVLO | input | Undervoltage lockout threshold set by resistor divider from VIN; typical on threshold 8.0 V, hysteresis 1 V. |+| 32 | PHSET | input | Master/slave mode and phase angle selection; master outputs 50% duty 2x clock, slave selects 0°/180° or 90°/270° phase shift. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | Power Management (PMIC) |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `TPS40322RHBR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `tps40322rhbr-etched.step` / `tps40322rhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps40322rhbr.step` / `tps40322rhbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps40322) (48 pp, sha256 `54a13b8f7fb2a2af`, retrieved 2026-10-06, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps40322rhbr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps40322rhbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps40322rhbr.kicad_sym",+ "tps40322rhbr.kicad_mod",+ "tps40322rhbr.glb",+ "tps40322rhbr.step",+ "tps40322rhbr.lbr",+ "docs/hero.png",+ "docs/tps40322rhbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps40322rhbr-hero.glb",+ "tps40322rhbr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS40322RHBR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Power Management (PMIC)",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps40322",+ "parts": {+ "symbol": "tps40322rhbr.kicad_sym",+ "footprint": "tps40322rhbr.kicad_mod",+ "model_3d": "tps40322rhbr-hero.glb",+ "model_3d_plain": "tps40322rhbr.glb",+ "model_3d_step": "tps40322rhbr-etched.step",+ "model_3d_step_plain": "tps40322rhbr.step",+ "lbr": "tps40322rhbr.lbr"+ },+ "distributor_links": {+ "lcsc": 2650257,+ "digikey": "296-48742-2-ND",+ "mouser": "595-TPS40322RHBR"+ },+ "distributor_check": {+ "checked_at": "2026-10-06T00:24:27Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-48742-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS40322RHBR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SYNC",+ "type": "bidirectional",+ "description": "Bidirectional synchronization pin; outputs 2x free running clock in master mode or syncs to external clock (±20% range) in slave mode with 50% duty cycle, must be left floating when unused."+ },+ {+ "number": "2",+ "name": "RT",+ "type": "input",+ "description": "Connect resistor from this pin to AGND to set oscillator frequency from 100 kHz to 1 MHz."+ },+ {+ "number": "3",+ "name": "EN1/SS1",+ "type": "input",+ "description": "Logic level enable input for CH1 (float=on, low=off); soft-start programming pin charged by internal 10 μA current source."+ },+ {+ "number": "4",+ "name": "FB1",+ "type": "input",+ "description": "Inverting input to error amplifier CH1; voltage equals internal 0.600 V reference under normal operation."+ },+ {+ "number": "5",+ "name": "COMP1",+ "type": "output",+ "description": "Output of error amplifier 1 and connection node for loop compensation network components."+ },+ {+ "number": "6",+ "name": "AGND",+ "type": "power_in",+ "description": "Low noise analog ground connection to controller."+ },+ {+ "number": "7",+ "name": "COMP2",+ "type": "output",+ "description": "Output of error amplifier 2 and connection node for loop compensation network components."+ },+ {+ "number": "8",+ "name": "FB2",+ "type": "input",+ "description": "Inverting input to error amplifier CH2; voltage equals internal 0.600 V reference; connecting to BP6 enables two-phase mode."+ },+ {+ "number": "9",+ "name": "DIFFO",+ "type": "output",+ "description": "Differential amplifier output; must float or tie to BP6 in dual-channel mode."+ },+ {+ "number": "10",+ "name": "EN2/SS2/GSNS",+ "type": "input",+ "description": "Logic level enable input for CH2 (float=on, low=off) with 10 μA soft-start charging current; functions as GSNS (negative sense terminal) in two-phase mode."+ },+ {+ "number": "11",+ "name": "ILIM2/VSNS",+ "type": "input",+ "description": "Set CH2 overcurrent limit using 10 μA from this pin to AGND; functions as VSNS (positive sense terminal) in two-phase mode."+ },+ {+ "number": "12",+ "name": "CS2–",+ "type": "input",+ "description": "Negative terminal of current sense amplifier for CH2; typical voltage drop < 50 mV."+ },+ {+ "number": "13",+ "name": "CS2+",+ "type": "input",+ "description": "Positive terminal of current sense amplifier for CH2; typical voltage drop < 50 mV."+ },+ {+ "number": "14",+ "name": "PG2",+ "type": "output",+ "description": "Open-drain power good indicator for CH2; pulls low if output ±12.5% from nominal or soft-start active."+ },+ {+ "number": "15",+ "name": "BOOT2",+ "type": "power_out",+ "description": "Bootstrap supply for high-side FET driver CH2; connect 0.1 μF capacitor from BOOT2 to SW2 with ripple <100 mV."+ },+ {+ "number": "16",+ "name": "HDRV2",+ "type": "output",+ "description": "Bootstrapped gate drive output for high-side N-channel MOSFET CH2; 2 Ω series resistor recommended in noisy environments."+ },+ {+ "number": "17",+ "name": "SW2",+ "type": "input",+ "description": "Connect to switched node voltage of CH2 converter; provides return path for high-side gate driver HDRV2."+ },+ {+ "number": "18",+ "name": "LDRV2",+ "type": "output",+ "description": "Gate drive output for low-side synchronous rectifier N-channel MOSFET CH2."+ },+ {+ "number": "19",+ "name": "PGND2",+ "type": "power_in",+ "description": "Power ground connection for CH2; separate PCB layout from PGND1 reduces channel-to-channel interference."+ },+ {+ "number": "20",+ "name": "BP6",+ "type": "power_out",+ "description": "Internal regulator 3.3 V bypass output; connect 3.3 μF minimum low-ESR ceramic capacitor to power ground plane."+ },+ {+ "number": "21",+ "name": "PGND1",+ "type": "power_in",+ "description": "Power ground connection for CH1; separate PCB layout from PGND2 reduces channel-to-channel interference."+ },+ {+ "number": "22",+ "name": "LDRV1",+ "type": "output",+ "description": "Gate drive output for low-side synchronous rectifier N-channel MOSFET CH1."+ },+ {+ "number": "23",+ "name": "SW1",+ "type": "input",+ "description": "Connect to switched node voltage of CH1 converter; provides return path for high-side gate driver HDRV1."+ },+ {+ "number": "24",+ "name": "HDRV1",+ "type": "output",+ "description": "Bootstrapped gate drive output for high-side N-channel MOSFET CH1; 2 Ω series resistor recommended in noisy environments."+ },+ {+ "number": "25",+ "name": "BOOT1",+ "type": "power_out",+ "description": "Bootstrap supply for high-side FET driver CH1; connect 0.1 μF capacitor from BOOT1 to SW1 with ripple <100 mV."+ },+ {+ "number": "26",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply input (3 V to 20 V); connect 0.1 μF minimum low-ESR bypass capacitor closely to AGND."+ },+ {+ "number": "27",+ "name": "PG1",+ "type": "output",+ "description": "Open-drain power good indicator for CH1; pulls low if output ±12.5% from nominal or soft-start active."+ },+ {+ "number": "28",+ "name": "CS1+",+ "type": "input",+ "description": "Positive terminal of current sense amplifier for CH1; typical voltage drop < 50 mV."+ },+ {+ "number": "29",+ "name": "CS1–",+ "type": "input",+ "description": "Negative terminal of current sense amplifier for CH1; typical voltage drop < 50 mV."+ },+ {+ "number": "30",+ "name": "ILIM1",+ "type": "input",+ "description": "Set CH1 overcurrent limit using 10 μA from this pin to AGND."+ },+ {+ "number": "31",+ "name": "UVLO",+ "type": "input",+ "description": "Undervoltage lockout threshold set by resistor divider from VIN; typical on threshold 8.0 V, hysteresis 1 V."+ },+ {+ "number": "32",+ "name": "PHSET",+ "type": "input",+ "description": "Master/slave mode and phase angle selection; master outputs 50% duty 2x clock, slave selects 0°/180° or 90°/270° phase shift."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: BOOT1 and BOOT2 pins are marked as input (I) in the datasheet Pin Functions table (page 4-5), but th; BP6 classified as power_out (internal regulator output); verify this matches intended ERC classifica",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 17,+ "cost_usd": 0.2309,+ "at": "2026-10-06T00:24:11"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps40322",+ "pages": 48,+ "sha256": "54a13b8f7fb2a2af",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}