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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS40322RHBR

Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)

TPS40322RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SYNC	bidirectional	Bidirectional synchronization pin; outputs 2x free running clock in master mode or syncs to external clock (±20% range) in slave mode with 50% duty cycle, must be left floating when unused.
2	RT	input	Connect resistor from this pin to AGND to set oscillator frequency from 100 kHz to 1 MHz.
3	EN1/SS1	input	Logic level enable input for CH1 (float=on, low=off); soft-start programming pin charged by internal 10 μA current source.
4	FB1	input	Inverting input to error amplifier CH1; voltage equals internal 0.600 V reference under normal operation.
5	COMP1	output	Output of error amplifier 1 and connection node for loop compensation network components.
6	AGND	power_in	Low noise analog ground connection to controller.
7	COMP2	output	Output of error amplifier 2 and connection node for loop compensation network components.
8	FB2	input	Inverting input to error amplifier CH2; voltage equals internal 0.600 V reference; connecting to BP6 enables two-phase mode.
9	DIFFO	output	Differential amplifier output; must float or tie to BP6 in dual-channel mode.
10	EN2/SS2/GSNS	input	Logic level enable input for CH2 (float=on, low=off) with 10 μA soft-start charging current; functions as GSNS (negative sense terminal) in two-phase mode.
11	ILIM2/VSNS	input	Set CH2 overcurrent limit using 10 μA from this pin to AGND; functions as VSNS (positive sense terminal) in two-phase mode.
12	CS2-	input	Negative terminal of current sense amplifier for CH2; typical voltage drop < 50 mV.
13	CS2+	input	Positive terminal of current sense amplifier for CH2; typical voltage drop < 50 mV.
14	PG2	output	Open-drain power good indicator for CH2; pulls low if output ±12.5% from nominal or soft-start active.
15	BOOT2	power_out	Bootstrap supply for high-side FET driver CH2; connect 0.1 μF capacitor from BOOT2 to SW2 with ripple <100 mV.
16	HDRV2	output	Bootstrapped gate drive output for high-side N-channel MOSFET CH2; 2 Ω series resistor recommended in noisy environments.
17	SW2	input	Connect to switched node voltage of CH2 converter; provides return path for high-side gate driver HDRV2.
18	LDRV2	output	Gate drive output for low-side synchronous rectifier N-channel MOSFET CH2.
19	PGND2	power_in	Power ground connection for CH2; separate PCB layout from PGND1 reduces channel-to-channel interference.
20	BP6	power_out	Internal regulator 3.3 V bypass output; connect 3.3 μF minimum low-ESR ceramic capacitor to power ground plane.
21	PGND1	power_in	Power ground connection for CH1; separate PCB layout from PGND2 reduces channel-to-channel interference.
22	LDRV1	output	Gate drive output for low-side synchronous rectifier N-channel MOSFET CH1.
23	SW1	input	Connect to switched node voltage of CH1 converter; provides return path for high-side gate driver HDRV1.
24	HDRV1	output	Bootstrapped gate drive output for high-side N-channel MOSFET CH1; 2 Ω series resistor recommended in noisy environments.
25	BOOT1	power_out	Bootstrap supply for high-side FET driver CH1; connect 0.1 μF capacitor from BOOT1 to SW1 with ripple <100 mV.
26	VDD	power_in	Power supply input (3 V to 20 V); connect 0.1 μF minimum low-ESR bypass capacitor closely to AGND.
27	PG1	output	Open-drain power good indicator for CH1; pulls low if output ±12.5% from nominal or soft-start active.
28	CS1+	input	Positive terminal of current sense amplifier for CH1; typical voltage drop < 50 mV.
29	CS1-	input	Negative terminal of current sense amplifier for CH1; typical voltage drop < 50 mV.
30	ILIM1	input	Set CH1 overcurrent limit using 10 μA from this pin to AGND.
31	UVLO	input	Undervoltage lockout threshold set by resistor divider from VIN; typical on threshold 8.0 V, hysteresis 1 V.
32	PHSET	input	Master/slave mode and phase angle selection; master outputs 50% duty 2x clock, slave selects 0°/180° or 90°/270° phase shift.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(5x5)
Category	Power Management (PMIC)
Pins	33

CAD (KiCad official)

Symbol: TPS40322RHBR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: tps40322rhbr-etched.step / tps40322rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40322rhbr.step / tps40322rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (48 pp, sha256 54a13b8f7fb2a2af, retrieved 2026-10-06, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF