component

TPS40303DRCR

Public Made by Adom

by adom

Texas Instruments DC-DC Controllers, WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chiptps40303drcrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers tps40303drcr: viewers · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
tps40303drcr-etched.glb Publish 0.1.0 · Ray 2d ago
tps40303drcr-etched.step tps40303drcr: factory component page (tier=mfr) · Ray 2d ago
tps40303drcr-hero.glb tps40303drcr: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
tps40303drcr-hero.overlay.json Publish 0.1.0 · Ray 2d ago
tps40303drcr.glb Publish 0.1.0 · Ray 2d ago
tps40303drcr.kicad_mod Publish 0.1.0 · Ray 2d ago
tps40303drcr.kicad_sym Publish 0.1.0 · Ray 2d ago
tps40303drcr.lbr Publish 0.1.0 · Ray 2d ago
tps40303drcr.step Publish 0.1.0 · Ray 2d ago

TPS40303DRCR

Texas Instruments · DC-DC Controllers · WSON-10-EP(3x3)

TPS40303DRCR from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power input to the controller (3 V to 20 V operating, 22 V absolute max); bypass to GND with a low ESR ceramic capacitor of at least 1 µF close to the device.
2 EN/SS input Logic-level enable and soft-start pin: floating turns the controller on, pulling low disables it, a capacitor to GND sets soft-start time using a 10 µA internal source, and an optional 267-kΩ resistor to BP enables FSS.
3 PGOOD output Open-drain power good output.
4 COMP output Output of the error amplifier and connection node for loop feedback components.
5 FB input Inverting input to the error amplifier; in normal operation its voltage equals the internal 600 mV reference.
6 BOOT power_in Gate drive voltage for the high-side N-channel MOSFET; a 0.1 µF capacitor (typical) connects between this pin and SW, with an optional Schottky diode from BP to BOOT for low input voltage operation.
7 HDRV output Bootstrapped gate drive output for the high-side N-channel MOSFET.
8 SW passive Sense line for the adaptive anti-cross conduction circuitry and common connection for the flying high-side FET driver.
9 LDRV/OC output Gate drive output for the low-side synchronous rectifier N-channel MOSFET; a resistor to GND sets the OCP voltage level using a 10 µA internal current source during calibration.
10 BP power_out Output bypass for the internal regulator; connect a low ESR ceramic capacitor of 1 µF or greater from this pin to GND.
11 GND power_in Thermal pad providing the electrical ground connection and a low thermal impedance path to the PCB; tie externally to a ground plane.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-10-EP(3x3)
Category Power Supply Chip
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
FB input voltage VFB 597 600 603 mV TJ = 25°C, 3 V < VVDD < 20 V 5
FB input voltage VFB 594 600 606 mV -40°C < TJ < 125°C, 3 V < VVDD < 20 V 5
Input supply voltage range VVDD 3 20 V 5
Shutdown supply current IDDSD 70 100 µA VEN/SS < 0.2 V 5
Quiescent, nonswitching IDDQ 2.5 3.5 mA Let EN/SS float, VFB = 1 V 5
High-level input voltage, EN/SS VIH 0.55 0.7 1 V 5
Low-level input voltage, EN/SS VIL 0.27 0.3 0.33 V 5
Soft-start source current ISS 8 10 12 µA 5
Soft-start voltage level VSS 0.4 0.8 1.3 V 5
BP output voltage VBP 6.2 6.5 6.8 V IBP = 10 mA 5
Regulator dropout voltage, VVDD, VBP VDO 70 110 mV IBP = 25 mA, VVDD = 3 V 5
PWM frequency TPS40303 fSW 270 300 330 kHz 3 V < VVDD < 20 V 5
Minimum controllable pulse width tON(min) 70 ns Ensured by design 5
Output driver dead time HDRV off to LDRV on tDEAD 5 25 35 ns HDRV off to LDRV on 5
Output driver dead time LDRV off to HDRV on tDEAD 5 25 30 ns LDRV off to HDRV on 5
Feedback upper voltage limit for PGOOD VOV 655 675 700 mV 5
Feedback lower voltage limit for PGOOD VUV 500 525 550 mV 5
PGOOD pulldown resistance RPGD 30 70 Ω VFB = 0 V, IFB = 5 mA 5
PGOOD leakage current IPGDLK 10 20 µA 550 mV < VFB < 655 mV, VPGOOD = 5 V 5
High-side driver pullup resistance RHDHI 0.8 1.5 2.5 Ω VBOOT, VSW = 5 V, IHDRV = -100 mA 6
High-side driver pulldown resistance RHDLO 0.5 1 2.2 Ω VBOOT, VSW = 5 V, IHDRV = 100 mA 6
Low-side driver pullup resistance RLDHI 0.8 1.5 2.5 Ω ILDRV = -100 mA 6
Low-side driver pulldown resistance RLDLO 0.35 0.6 1.2 Ω ILDRV = 100 mA 6
OC threshold for high-side FET VOCH 360 450 580 mV TJ = 25°C 6
OCSET current source IOCSET 9.5 10 10.5 µA TJ = 25°C 6
Maximum clamp voltage at LDRV VLD-CLAMP 260 340 400 mV 6
OC comparator offset voltage for low-side FET VOCLOS -8 8 mV TJ = 25°C 6
Programmable OC range for low-side FET VOCLPRO 12 300 mV TJ = 25°C 6
OC threshold temperature coefficient VTHTC 3000 ppm both high-side and low-side 6
Bootstrap diode forward voltage VDFWD 0.8 V IBOOT = 5 mA 6
Junction shutdown temperature TJSD 145 °C 6
Supply voltage VDD VDD -0.3 22 V 4
SW voltage SW -3 27 V 4
SW voltage pulse SW -5 V < 100-ns pulse width, 10 µJ 4
BOOT voltage BOOT -0.3 30 V 4
HDRV voltage HDRV -5 30 V 4
BOOT-SW, HDRV-SW differential -0.3 7 V differential from BOOT or HDRV to SW 4
COMP, PGOOD, FB, BP, LDRV, EN/SS voltage -0.3 7 V 4
Operating junction temperature TJ -40 145 °C 4
Storage temperature Tstg -55 150 °C 4
ESD HBM V(ESD) -2000 2000 V Human-body model, ANSI/ESDA/JEDEC JS-001 4
ESD CDM V(ESD) -1500 1500 V Charged-device model, JESD22-C101 4
Input voltage VDD 3 20 V 4
Operating junction temperature TJ -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 44.3 °C/W DRC (VSON) 10 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 56.1 °C/W 4
Junction-to-board thermal resistance RθJB 19.2 °C/W 4
Junction-to-top characterization parameter ψJT 0.7 °C/W 4
Junction-to-board characterization parameter ψJB 19.4 °C/W 4
Junction-to-case (bottom) thermal resistance RθJC(bot) 5.5 °C/W 4

CAD (KiCad official)

  • Symbol: TPS40303DRCR
  • Footprint: Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm
  • 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps40303drcr-etched.step / tps40303drcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40303drcr.step / tps40303drcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 d41d25bea2bc30ba, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF