component
TPS40210DGQ
Public Made by Adomby adom
Texas Instruments DC-DC Converters, MSOP-10-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS40210DGQ
Texas Instruments · DC-DC Converters · MSOP-10-EP
TPS40210DGQ from Texas Instruments, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC | input | Oscillator timing pin: a resistor from RC to VDD and a capacitor from RC to GND set the switching frequency (35 kHz to 1000 kHz range), and RC must be pulled below 150 mV for at least 20 ns to synchronize to an external clock. |
| 2 | SS | input | Soft-start pin: a capacitor from SS to GND sets the closed-loop soft-start time and also serves as the restart timer during overcurrent faults. |
| 3 | DIS/EN | input | Active-high disable input: pulling it above the 1.2 V typical threshold shuts the controller down and turns off the BP regulator, while leaving it open enables the device. |
| 4 | COMP | output | Error amplifier output: the loop compensation network is connected between COMP and FB. |
| 5 | FB | input | Error amplifier inverting input: a divider from the output sets the output voltage, with a 700 mV typical reference for TPS40210 (the TPS40211 uses 260 mV). |
| 6 | GND | power_in | Device ground; the VDD and BP bypass capacitors must return to this pin. |
| 7 | ISNS | input | Current sense input: an external sense resistor is connected between ISNS and GND, and the overcurrent threshold is 150 mV typical; absolute maximum voltage is 8 V. |
| 8 | GDRV | output | Gate driver output that drives the gate of the external power N-channel MOSFET, with a 400 mA typical gate drive rating; absolute maximum is 9 V. |
| 9 | BP | power_out | Internal linear regulator output of 8 V nominal that must be bypassed with a 1.0 µF capacitor to GND and powers the controller's internal circuitry including the gate driver. |
| 10 | VDD | power_in | System input supply operating from 4.5 V to 52 V (absolute maximum 52 V), which must be bypassed close to GND. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-10-EP |
| Category | Power Management (PMIC) |
| Pins | 11 |
CAD (KiCad official)
- Symbol:
TPS40210DGQ - Footprint:
Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm - 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files:
tps40210dgq-etched.step/tps40210dgq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps40210dgq.step/tps40210dgq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (50 pp, sha256
7213a870ac0ef0d9, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).