main
Download ZIP Propose a change
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 20h ago
viewers tps40200drbr: viewers · Ray 20h ago
package.json Publish 0.1.0 · Ray 20h ago
page.json Set visibility: public · Ray 20h ago
README.md Initial commit: component/tps40200drbr · Ray 20h ago
tps40200drbr-etched.glb tps40200drbr: factory component page (tier=lcsc) · Ray 20h ago
tps40200drbr-etched.step tps40200drbr: factory component page (tier=lcsc) · Ray 20h ago
tps40200drbr-hero.glb Publish 0.1.0 · Ray 20h ago
tps40200drbr-hero.overlay.json Publish 0.1.0 · Ray 20h ago
tps40200drbr.glb Publish 0.1.0 · Ray 20h ago
tps40200drbr.kicad_mod Publish 0.1.0 · Ray 20h ago
tps40200drbr.kicad_sym Publish 0.1.0 · Ray 20h ago
tps40200drbr.lbr Publish 0.1.0 · Ray 20h ago
tps40200drbr.step Publish 0.1.0 · Ray 20h ago

TPS40200DRBR

Texas Instruments · DC-DC Converters · SON-8-EP(3x3)

TPS40200DRBR from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RC input Switching frequency setting RC network; connect capacitor from RC to GND and resistor from VDD to RC; device may be synchronized to external clock by connecting open drain output to this pin and pulling it to GND.
2 SS input Soft-start programming pin; connect capacitor from SS to GND to program soft start time; pulling below 150 mV stops output switching and places device in shutdown state; functions as restart timer for overcurrent events.
3 COMP output Error amplifier output; connect control loop compensation network from COMP to FB.
4 FB input Error amplifier inverting input; connect feedback resistor network center tap to this pin.
5 GND power_in Device ground.
6 GDRV output Driver output for external P-channel MOSFET; 200-mA internal driver.
7 ISNS input Current-sense comparator input; connect current sense resistor between ISNS and VDD to set desired overcurrent threshold.
8 VDD power_in System input voltage, operating range 4.5 V to 52 V; connect local bypass capacitor from VDD to GND.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SON-8-EP(3x3)
Category Power Management (PMIC)
Pins 9

CAD (KiCad official)

  • Symbol: TPS40200DRBR
  • Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
  • 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps40200drbr-etched.step / tps40200drbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40200drbr.step / tps40200drbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 a3e23ec7367038ec, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF