component
TPS40200DR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS40200DR
Texas Instruments · DC-DC Converters · SOIC-8
TPS40200DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC | input | Switching frequency setting input via external RC network for operation between 35 kHz and 500 kHz, or external clock synchronization input with pulse amplitude greater than VIN/10 and minimum 150 mV trigger threshold. |
| 2 | SS | input | Soft-start programming input; external capacitor to GND determines soft-start interval; voltage pulled below 150 mV disables switching and places device in shutdown state. |
| 3 | COMP | output | Error amplifier output for control loop compensation network connection to FB pin. |
| 4 | FB | input | Error amplifier inverting input; connect feedback resistor network center tap to establish regulated output voltage. |
| 5 | GND | power_in | Device ground reference. |
| 6 | GDRV | output | Gate driver output for external P-channel MOSFET; output voltage 6 V to 10 V with pull-up current 125-300 mA and pull-down current 200-300 mA. |
| 7 | ISNS | input | Current-sense comparator input with 100 mV nominal threshold; connect current sense resistor between ISNS and VDD to set overcurrent protection level. |
| 8 | VDD | power_in | System power supply input operating range 4.5 V to 52 V; local bypass capacitor to GND required for proper operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback voltage (COMP = FB, TA = 25°C) | VFB | 689 | 696 | 702 | mV | COMP = FB, TA = 25°C | 5 |
| Feedback voltage (TA = 25°C) | VFB | 686 | 696 | 703 | mV | TA = 25°C | 5 |
| Feedback voltage (over VDD and 85°C range) | VFB | 679 | 696 | 708 | mV | 4.5 < VDD < 52, –40°C < TA < 85°C | 5 |
| Feedback voltage (full temperature range) | VFB | 679 | 696 | 710 | mV | –40°C < TA < 125°C | 5 |
| Gate driver pull-up current | Isrc | 125 | 300 | mA | 5 | ||
| Gate driver pull-down current | Isnk | 200 | 300 | mA | 5 | ||
| Gate driver output voltage | VGATE | 6 | 8 | 10 | V | VGATE = (VDD – VGDRV), for 12 < VDD < 52 | 5 |
| Device quiescent current | Iqq | 1.5 | 3 | mA | fOSC = 300 kHz, Driver not switching, 4.5 < VDD < 52 | 5 | |
| UVLO turn-on threshold | VUVLO(on) | 3.8 | 4.25 | 4.5 | V | –40°C < TA < 125°C | 5 |
| UVLO turn-off threshold | VUVLO(off) | 4.05 | V | 5 | |||
| UVLO hysteresis | VUVLO(HYST) | 110 | 200 | 275 | mV | 5 | |
| Internal soft-start pull-up resistance | RSS(chg) | 65 | 105 | 170 | kΩ | 5 | |
| Internal soft-start pull-down resistance | RSS(dchg) | 190 | 305 | 485 | kΩ | 5 | |
| Soft-start reset threshold | VSSRST | 100 | 150 | 200 | mV | 5 | |
| Overcurrent threshold | VILIM | 65 | 100 | 140 | mV | 0°C < TA < 125°C | 5 |
| Overcurrent threshold | VILIM | 55 | 100 | 140 | mV | 4.5 < VDD < 52, –40°C < TA < 125°C | 5 |
| Overcurrent reset threshold | VILIM(rst) | 100 | 150 | 200 | mV | 5 | |
| Oscillator frequency range | 35 | 500 | kHz | 5 | |||
| Oscillator frequency | fOSC | 85 | 100 | 115 | kHz | RRC = 200 kΩ, CRC = 470 pF | 5 |
| Oscillator frequency | fOSC | 255 | 300 | 345 | kHz | RRC = 68.1 kΩ, CRC = 470 pF | 5 |
| Frequency line regulation | -9 | 0 | % | 12 V < VDD < 52 V | 5 | ||
| Frequency line regulation | -20 | 0 | % | 4.5 V < VDD < 12 V | 5 | ||
| Minimum controllable pulse width | tMIN | 200 | 400 | ns | VDD = 12 V | 6 | |
| Minimum controllable pulse width | tMIN | 100 | 200 | ns | VDD = 30 V | 6 | |
| Maximum duty cycle | DMAX | 93 | 95 | % | fosc = 100 kHz, CL = 470 pF | 6 | |
| Maximum duty cycle | DMAX | 90 | 93 | % | fosc = 300 kHz, CL = 470 pF | 6 | |
| Modulator and power stage DC gain | KPWM | 8 | 10 | 12 | V/V | 6 | |
| Input bias current | IIB | 100 | 250 | nA | 6 | ||
| Open loop gain | AOL | 60 | 80 | dB | 6 | ||
| Unity gain bandwidth | GBWP | 1.5 | 3 | MHz | 6 | ||
| Output source current | ICOMP(src) | 100 | 250 | µA | VFB = 0.6 V, COMP = 1 V | 6 | |
| Output sink current | ICOMP(snk) | 1 | 2.5 | mA | VFB = 1.2 V, COMP = 1 V | 6 | |
| Input voltage (VDD) | VDD | 4.5 | 52 | V | 4 | ||
| Operating temperature range (TJ) | TJ | -40 | 125 | °C | 4 | ||
| Input voltage range (VDD, ISNS) | VDD, ISNS | -0.3 | 52 | V | over operating free-air temperature range | 4 | |
| Input voltage range (RC, FB) | RC, FB | -0.3 | 5.5 | V | over operating free-air temperature range | 4 | |
| Output voltage range (SS) | SS | -0.3 | 9 | V | over operating free-air temperature range | 4 | |
| Output voltage range (COMP) | COMP | -0.3 | 9 | V | over operating free-air temperature range | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Lead temperature | 260 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 4 | |||
| Storage temperature range | Tstg | -55 | 150 | °C | 4 | ||
| Electrostatic discharge, human body model | V(ESD) | -1500 | 1500 | V | HBM, per ANSI/ESDA/JEDEC JS-001, all pins | 4 | |
| Electrostatic discharge, charged device model | V(ESD) | -1500 | 1500 | V | CDM, per JEDEC JESD22-C101, all pins | 4 | |
| Junction-to-ambient thermal resistance (SOIC, D) | RθJA | 109.6 | °C/W | SOIC (D) 8-pin package | 4 | ||
| Junction-to-case (top) thermal resistance (SOIC, D) | RθJC(top) | 54 | °C/W | SOIC (D) 8-pin package | 4 | ||
| Junction-to-board thermal resistance (SOIC, D) | RθJB | 49.6 | °C/W | SOIC (D) 8-pin package | 4 | ||
| Junction-to-top characterization parameter (SOIC, D) | ψJT | 11.2 | °C/W | SOIC (D) 8-pin package | 4 | ||
| Junction-to-board characterization parameter (SOIC, D) | ψJB | 49.1 | °C/W | SOIC (D) 8-pin package | 4 |
CAD (KiCad official)
- Symbol:
TPS40200DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps40200dr-etched.step/tps40200dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps40200dr.step/tps40200dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
a3e23ec7367038ec, retrieved 2026-09-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).