TPS40195PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Logic-level enable input; a high level turns the controller on and the pin must be pulled below 600 mV to enter shutdown, with a weak internal pull-up holding it high when floating.
2	FB	input	Inverting input to the error amplifier, which in normal operation sits at the internal 591 mV typical reference voltage.
3	COMP	output	Output of the error amplifier.
4	VDD	power_in	Power input to the controller, specified from 4.5 V to 20 V, with a 100-nF bypass capacitor to GND placed close to the pin.
5	UVLO	input	Programmable undervoltage lockout pin; a resistor divider from VDD sets the turn-on voltage (1.26 V threshold) and the hysteresis via a 5.2 µA current source.
6	RT	input	Switching frequency programming pin; a resistor to GND sets 100 kHz to 600 kHz, while connection to GND or BP fixes 250 kHz or 500 kHz with SYNC as an output.
7	ILIM	input	Current limit pin that sets the low-side MOSFET overcurrent threshold through a resistor connected to GND.
8	GND	power_in	Common reference ground for the device.
9	SYNC	bidirectional	Bidirectional synchronization pin that is an output (falling edge 180° out of phase with HDRV) when RT is tied to GND or BP, and an input synchronizing to the falling edge of an external clock when RT is resistor-programmed; connect to GND if unused.
10	PGOOD	output	Open-drain power good output that is pulled low during any fault, during soft start, or when the FB voltage is outside the specified window.
11	SS_SEL	input	Soft-start timing selection pin, connected to GND, BP, or left floating to select 2048, 1024, or 512 DAC clock cycles respectively.
12	BP	power_out	Output bypass for the internal regulator, requiring a capacitor of 1 µF or greater to GND, up to 4.7 µF for improved noise performance; not to be connected to VDD or driven externally.
13	LDRV	output	Gate drive output for the low-side N-channel FET.
14	BOOT	input	Gate drive voltage for the high-side N-channel MOSFET, requiring a 100-nF typical capacitor connected between this pin and SW.
15	SW	input	Sense line for the adaptive anti-cross conduction circuitry and common connection for the flying high-side MOSFET driver.
16	HDRV	output	Gate drive output to the high-side N-channel FET.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Power Management (PMIC)
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage range	VVDD	4.5		20	V		5
Operating junction temperature	TJ	-40		125	°C		5
Input voltage	VDD	-0.3		22	V		5
Input voltage	SW	-5		25	V		5
Input voltage	BOOT	-0.3		30	V		5
Input voltage	HDRV	-5		30	V		5
Differential voltage	BOOT-SW, HDRV-SW	-0.3		6	V	Differential from BOOT or HDRV to SW	5
Input voltage	EN, FB, BP, LDRV, PGOOD, ILIM, SYNC, UVLO, SS_SEL, RT	-0.3		6	V		5
Input voltage	COMP	-0.3		3	V		5
Operating junction temperature	TJ	-40		150	°C		5
Storage temperature	Tstg	-55		150	°C		5
Junction-to-ambient thermal resistance (PW package)	RθJA		110		°C/W	PW package, 0 LFM natural convection, High-K board	7
Feedback voltage range	VFB	588	591	594	mV	0°C ≤ TJ ≤ 85°C	6
Feedback voltage range	VFB	585	591	594	mV	-40°C ≤ TJ ≤ 85°C	6
Operating current	IVDD			4	mA	VEN = 3 V	6
Operating current	IVDD		165	250	μA	VEN < 0.6 V, VVDD = 12 V	6
Operating current	IVDD		230	330	μA	VEN < 0.6 V, VVDD = 20 V	6
Output voltage	VBP	5.1	5.3	5.5	V	VVDD > 6 V, IBP ≤ 10 mA	6
Regulator dropout voltage, VVDD - VBP	VDO		350	550	mV	VVDD = 5 V, IBP ≤ 25 mA	6
Regulator current limit threshold	ISC			75	mA		6
Average current	IBP			75	mA		6
Switching frequency	fSW	400	500	580	kHz	VRT = VBP	6
Switching frequency	fSW	200	250	290	kHz	VRT = 0 V	6
High-level input voltage	VINH	2.5			V		6
Low-level input voltage	VINL			0.5	V		6
Maximum input fall time	TF(max)			100	ns		6
High-level output voltage	VOH	3.5			V	ISYNC = 100 μA, sourcing	6
Low-level output voltage	VOL			0.3	V	ISYNC = 100 μA, sinking	6
Output fall time	TF		10	25	ns	CSYNC = 25 pF	6
Output rise time	TR		100	300	ns		6
Maximum duty cycle	DMAX			85	%		6
Minimum controlled pulse	tON(min)			130	ns		6
Output driver dead time	tDEAD			50	ns	HDRV off to LDRV on	6
Output driver dead time	tDEAD			25	ns	LDRV off to HDRV on	6
Soft-start time	tSS		4.8		ms	VSS_SEL = 0 V, fSW = 250 kHz	6
Soft-start time	tSS		2.4		ms	VSS_SEL = 0 V, fSW = 500 kHz	6
Soft-start time	tSS		1.2		ms	VSS_SEL = Floating, fSW = 500 kHz	6
Soft-start time	tSS		0.6		ms	VSS_SEL = VBP, fSW = 500 kHz	6
Gain bandwidth product	GBWP		7	10	MHz		6
DC gain	AOL	60			dB		6
Input bias current (current out of FB pin)	IFB			100	nA		6
Output source current	IEAOP	1			mA	VFB = 0 V	6
Output sink current	IEAOM	1			mA	VFB = 2 V	6
Minimum pulse during short circuit	tPSS(min)	250			ns		7
Blanking time	tBLNK	60	90	120	ns		7
ILIM pin bias current	IILIM	7	9	11	μA	TJ = 25°C	7
Low side comparator offset voltage	VILIMOFST	-20	0	20	mV		7
Short circuit threshold voltage on high-side MOSFET	VILIMH	400	550	650	mV	TJ = 25°C	7
High-side driver pull-up resistance	RHDHI		3	6	Ω	VBOOT - VSW = 4.5 V, IHDRV = -100 mA	7
High-side driver pull-down resistance	RHDLO		1.5	3	Ω	VBOOT - VSW = 4.5 V, IHDRV = 100 mA	7
Low-side driver pull-up resistance	RLDHI		2.5	5	Ω	ILDRV = -100 mA	7
Low-side driver pull-down resistance	RLDLO		0.8	1.5	Ω	ILDRV = 100 mA	7
BP5 UVLO threshold voltage	VUVLOBP	3.9	4.1	4.3	V		7
Turn-on voltage	VUVLO	1.125	1.26	1.375	V		7
High-level input voltage, EN	VIH	1.9		3	V		7
Low-level input voltage, EN	VIL			0.6	V		7
Feedback voltage limit for power good	VOV			650	mV		7
Feedback voltage limit for power good	VUV			530	mV		7
Bootstrap diode forward voltage	VDFWD	0.5	0.8	1.2	V	IBOOT = 5 mA	7
Junction shutdown temperature	TJSDH		20		°C	Hysteresis	7

CAD (KiCad official)

Symbol: TPS40195PWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: tps40195pwr-etched.step / tps40195pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40195pwr.step / tps40195pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (47 pp, sha256 f9ecda370c4be9f6, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS40195PWR

Verified TPS40195PWR

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3D Model

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