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TPS40101RGER

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Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS40101RGER

Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)

TPS40101RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier output that connects through a feedback network to FB for control-loop compensation.
2 FB input Inverting error amplifier input that sits at the internal reference of approximately 690 mV in normal operation.
3 TRKOUT output Tracking amplifier output that, when tracking is used, connects to FB through a resistor in series with a low-leakage diode.
4 TRKIN input Tracking control input; the output tracks TRKIN with a typical offset of 25 mV when the tracking amplifier is used.
5 UVLO input Programs the undervoltage lockout level and serves as the device shutdown input.
6 ILIM output Sets the overcurrent threshold through a resistor to GND; overcurrent is declared when this voltage reaches 1.48 V, and a parallel capacitor adds a nuisance-trip delay.
7 RT input A resistor from this pin to GND sets the operating frequency.
8 BIAS power_out Bypassed supply for internal circuitry; a 0.1-µF or greater ceramic capacitor should be connected from this pin to GND.
9 GND power_in Low-power signal ground; all signal-level circuits should be referenced to this pin unless otherwise noted.
10 SS input Soft-start programming pin; a capacitor to ground sets the soft-start time, and the pin also serves as a timeout during an overcurrent event.
11 GM input A resistor from this pin to GND sets the gain of the current sense amplifier.
12 PGND power_in Power ground for the internal gate drivers.
13 LDRV output Gate drive output for the N-channel synchronous rectifier MOSFET.
14 5VBP power_out Output of the internal 5-V regulator, bypassed with 1 µF to PGND; total gate drive and external load current must not exceed the device thermal capability.
15 BST input Gate drive supply for the high-side N-channel MOSFET; an external Schottky diode from 5VBP (anode) to BST (cathode) and a capacitor from BST to SW are required.
16 HDRV output Floating gate drive output for the high-side N-channel MOSFET.
17 SW input Connected to the switched node of the converter; the return line for the flying high-side driver.
18 VDD power_in Supply voltage for the device; operation is specified from 4.5 V to 18 V, with an absolute maximum of -0.3 V to 20 V.
19 ISNS input Inductor DCR sensing input to the current sense amplifier used for overcurrent detection.
20 VO input Output voltage sense input and reference input to the current sense amplifier.
21 PG output Open-drain power-good output that is pulled low when FB is more than 10% above or below 690 mV, during UVLO, soft-start, tracking, overcurrent, or over-temperature.
22 SYNC input Rising-edge synchronization input for an external master clock; may be left floating or grounded if unused.
23 MGD input Margin-down pin; pulling to GND through less than 10 kΩ lowers the output by 5%, and a 30-kΩ resistor to GND gives a 3% margin.
24 MGU input Margin-up pin; pulling to GND through less than 10 kΩ raises the output by 5%, and a 30-kΩ resistor to GND gives a 3% margin.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD (absolute maximum) VDD -0.3 20 V 2
Input/output voltage, 5VBP, BIAS, FB, ILIM, ISNS, LDRV, MGU, MGD, PG, SS, SYNC, UVLO, VO -0.3 6 V 2
BST to SW, HDRV to SW voltage -0.3 6 V relative to SW 2
SW input voltage range VIN -1.5 V 2
SW transient voltage -6 30 V transient < 100 ns 2
TRKIN input voltage -0.3 20 V 2
GND to PGND voltage -0.3 0.3 V 2
TRKOUT voltage -0.3 8 V 2
HDRV, LDRV RMS current 0.5 A RMS 2
HDRV, LDRV peak current 2 A peak 2
FB, COMP, TRKOUT input current range IIN -10 10 mA 2
SS input current range IIN -20 20 mA 2
PG input current range IIN 20 mA 2
GM input current range IIN 1 mA 2
RT input current range IIN 10 mA 2
V5BP output current V5BP 50 mA includes gate drive current requirements 2
Operating junction temperature range TJ -40 125 °C 2
Storage temperature range Tstg -55 150 °C 2
Operating free-air temperature range TA -40 85 °C ordering table, QFN package 2
Operating range (input voltage) VDD 4.5 18 V 3
Quiescent current IDD 1.3 1.8 2.5 mA VFB > 0.8 V, 0% duty cycle 3
Internal regulator voltage (5VBP) 4.7 5 5.3 V 7 V ≤ VVDD ≤ 18 V, 0 mA ≤ ILOAD ≤ 30 mA 3
Internal regulator voltage (5VBP) 4.3 5 5.3 V 4.5 V ≤ VVDD < 7 V, 0 mA ≤ ILOAD ≤ 30 mA 3
Programmable oscillator frequency fSW 100 1000 kHz 3
Oscillator frequency accuracy fOSC 250 275 300 kHz 4.5 V ≤ VIN < 18 V, -40°C ≤ TA = TJ ≤ 125°C 3
Valley voltage VVLY 1 1.6 2 V 3
High-level input voltage, SYNC VIH 2 V 3
Low-level input voltage, SYNC VIL 0.8 V 3
Input current, SYNC ISYNC 4 5.5 10 µA VSYNC = 2.5 V 3
Soft-start source (charge) current ISS 13 20 25 µA 3
Soft-start sink (discharge) current ISS_SINK 3.4 5 6.6 µA 3
Soft-start completed voltage VSSC 3.25 3.4 3.75 V 3
Soft-start discharged voltage VSSD 0.15 0.2 0.25 V 3
Offset from SS to error amplifier VSSOS 300 500 800 mV 3
Feedback voltage reference VFB 686 690 694 mV TA = TJ = 25°C 3
Feedback voltage reference VFB 683 697 mV -40°C < TA = TJ ≤ 125°C 3
Feedback voltage margin 5% up VFBMGU 715 725 735 mV VMGU ≤ 500 mV 4
Feedback voltage margin 3% up VFBMGU 700 711 720 mV 2 V ≤ VMGU ≤ 3 V 4
Feedback voltage margin 5% down VFBMGD 645 655 665 mV VMGD ≤ 500 mV 4
Feedback voltage margin 3% down VFBMGD 660 669 680 mV 2 V ≤ VMGD ≤ 3 V 4
Margin-up bias current IMGUP 60 80 100 µA 4
Margin-down bias current IMGDN 60 80 100 µA 4
Current sense amplifier gain gmCSA 300 333 365 µS TJ = 25°C 4
Gm linear range voltage VGMLIN -50 50 mV TJ = 25°C 4
Input voltage common mode VGMCM 0 3.6 V 4.5 V ≤ VIN ≤ 5.5 V 5
ILIM pin voltage to trip overcurrent VILIM 1.44 1.48 1.52 V 4
Current limit comparator propagation delay tILIMDLY 70 140 ns HDRV transition from on to off 4
High-side driver pullup resistance RHDRVUP 2.4 4 Ω IHDRV = 300 mA 4
High-side driver pulldown resistance RHDRVDN 1 1.8 Ω IHDRV = 300 mA 4
Low-side driver pullup resistance RLDRVUP 2 4 Ω ILDRV = 300 mA 4
Low-side driver pulldown resistance RLDRVDN 0.8 1.5 Ω ILDRV = 300 mA 4
Leakage current from SW pin ISWLEAK -1 1 µA 4
Powergood low voltage VLPGD 30 100 mV IPGD = 2 mA 4
Powergood low voltage, no device power VLPGDNP 1 1.25 V VVDD = OPEN, 10-kΩ pullup to external 5-V supply 4
Tracking amplifier input offset voltage VTRKOS 7 25 40 mV VVO ≤ 2 V 5
Tracking amplifier input offset voltage VTRKOS -5 25 40 mV 2 V < VVO ≤ 6 V 5
Undervoltage lockout threshold (programmable) VUVLO 1.285 1.332 1.378 V 5
Fixed UVLO turn-on voltage at VDD pin VUVLOFON 3.85 4.15 4.425 V -40°C ≤ TA < 125°C 5
Thermal shutdown temperature TSD 130 165 °C 5
Gain temperature coefficient, current sense amplifier TCGM -2000 ppm/°C 4

CAD (KiCad official)

  • Symbol: TPS40101RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps40101rger-etched.step / tps40101rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40101rger.step / tps40101rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 7d2f9600d1852106, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF