TPS40100RGER

Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)

TPS40100RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Output of the error amplifier; a feedback network connected from this pin to FB provides control loop compensation.
2	FB	input	Inverting input to the error amplifier; in normal operation its voltage equals the internal reference of approximately 690 mV.
3	TRKOUT	output	Output of the tracking amplifier; when tracking is used, connect to FB through a resistor in series with a low-leakage diode.
4	TRKIN	input	Control input for simultaneous startup of multiple controllers; the output tracks TRKIN with a controlled offset, typically 25 mV, when the tracking amplifier is used.
5	UVLO	input	Programs the undervoltage lockout level and serves as the shutdown input for the device.
6	ILIM	output	Sets the overcurrent threshold through a resistor to GND; an overcurrent condition is declared when the voltage reaches 1.48 V, and a parallel capacitor can add a delay to avoid nuisance trips.
7	RT	input	A resistor connected from this pin to GND sets the operating frequency.
8	BIAS	output	Bypassed supply for internal device circuitry; connect a 0.1-µF or greater ceramic capacitor from this pin to GND.
9	GND	power_in	Low-power or signal ground; all signal-level circuits are referenced to this pin unless otherwise noted.
10	SS	input	Soft-start programming pin; a capacitor from this pin to ground sets the soft-start time and it also acts as a timeout during an overcurrent event.
11	GM	input	Connect a resistor from this pin to GND to set the gain of the current sense amplifier.
12	PGND	power_in	Power ground for the internal gate drivers.
13	LDRV	output	Gate drive for the N-channel synchronous rectifier MOSFET.
14	5VBP	output	Output of the internal 5-V regulator; a 1-µF bypass capacitor is connected from this pin to PGND, and total gate drive plus external current draw must not exceed the thermal capability of the device.
15	BST	input	Gate drive voltage supply for the high-side N-channel MOSFET; an external Schottky diode from 5VBP (anode) to BST (cathode) and a capacitor from BST to SW are required.
16	HDRV	output	Floating gate drive for the high-side N-channel MOSFET.
17	SW	input	Connected to the switched node of the converter; it is the return line for the floating high-side driver.
18	VDD	power_in	Supply voltage for the device; absolute maximum rating is -0.3 V to 20 V.
19	ISNS	input	Input from the inductor DCR sensing network, serving as one input to the current sense amplifier for current feedback control and overcurrent protection.
20	VO	input	Output voltage sense input; it is the reference input to the current sense amplifier for current mode control and overcurrent protection.
21	PG	output	Open-drain power good output that is pulled low when FB is more than 10% above or below 690 mV, during UVLO, soft-start, tracking, overcurrent, or over-temperature.
22	SYNC	input	Rising-edge trigger that synchronizes the oscillator to an external master clock; it may be left floating or grounded if unused.
23	MGD	input	Margin-down pin for load stress test; pulling it to GND through less than 10 kΩ lowers the output by 5%, and a 30-kΩ connection to GND gives a 3% margin down.
24	MGU	input	Margin-up pin for load stress test; pulling it to GND through less than 10 kΩ raises the output by 5%, and a 30-kΩ connection to GND gives a 3% margin up.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	Power Management (PMIC)
Pins	25

CAD (KiCad official)

Symbol: TPS40100RGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: tps40100rger-etched.step / tps40100rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40100rger.step / tps40100rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (41 pp, sha256 022e07b23118d8ca, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPS40100RGER

**Texas Instruments** · DC-DC Converters · VQFN-24-EP(4x4)

TPS40100RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Output of the error amplifier; a feedback network connected from this pin to FB provides control loop compensation. |
| 2 | FB | input | Inverting input to the error amplifier; in normal operation its voltage equals the internal reference of approximately 690 mV. |
| 3 | TRKOUT | output | Output of the tracking amplifier; when tracking is used, connect to FB through a resistor in series with a low-leakage diode. |
| 4 | TRKIN | input | Control input for simultaneous startup of multiple controllers; the output tracks TRKIN with a controlled offset, typically 25 mV, when the tracking amplifier is used. |
| 5 | UVLO | input | Programs the undervoltage lockout level and serves as the shutdown input for the device. |
| 6 | ILIM | output | Sets the overcurrent threshold through a resistor to GND; an overcurrent condition is declared when the voltage reaches 1.48 V, and a parallel capacitor can add a delay to avoid nuisance trips. |
| 7 | RT | input | A resistor connected from this pin to GND sets the operating frequency. |
| 8 | BIAS | output | Bypassed supply for internal device circuitry; connect a 0.1-µF or greater ceramic capacitor from this pin to GND. |
| 9 | GND | power_in | Low-power or signal ground; all signal-level circuits are referenced to this pin unless otherwise noted. |
| 10 | SS | input | Soft-start programming pin; a capacitor from this pin to ground sets the soft-start time and it also acts as a timeout during an overcurrent event. |
| 11 | GM | input | Connect a resistor from this pin to GND to set the gain of the current sense amplifier. |
| 12 | PGND | power_in | Power ground for the internal gate drivers. |
| 13 | LDRV | output | Gate drive for the N-channel synchronous rectifier MOSFET. |
| 14 | 5VBP | output | Output of the internal 5-V regulator; a 1-µF bypass capacitor is connected from this pin to PGND, and total gate drive plus external current draw must not exceed the thermal capability of the device. |
| 15 | BST | input | Gate drive voltage supply for the high-side N-channel MOSFET; an external Schottky diode from 5VBP (anode) to BST (cathode) and a capacitor from BST to SW are required. |
| 16 | HDRV | output | Floating gate drive for the high-side N-channel MOSFET. |
| 17 | SW | input | Connected to the switched node of the converter; it is the return line for the floating high-side driver. |
| 18 | VDD | power_in | Supply voltage for the device; absolute maximum rating is -0.3 V to 20 V. |
| 19 | ISNS | input | Input from the inductor DCR sensing network, serving as one input to the current sense amplifier for current feedback control and overcurrent protection. |
| 20 | VO | input | Output voltage sense input; it is the reference input to the current sense amplifier for current mode control and overcurrent protection. |
| 21 | PG | output | Open-drain power good output that is pulled low when FB is more than 10% above or below 690 mV, during UVLO, soft-start, tracking, overcurrent, or over-temperature. |
| 22 | SYNC | input | Rising-edge trigger that synchronizes the oscillator to an external master clock; it may be left floating or grounded if unused. |
| 23 | MGD | input | Margin-down pin for load stress test; pulling it to GND through less than 10 kΩ lowers the output by 5%, and a 30-kΩ connection to GND gives a 3% margin down. |
| 24 | MGU | input | Margin-up pin for load stress test; pulling it to GND through less than 10 kΩ raises the output by 5%, and a 30-kΩ connection to GND gives a 3% margin up. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |

## CAD (KiCad official)

- Symbol: `TPS40100RGER`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`
- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `tps40100rger-etched.step` / `tps40100rger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps40100rger.step` / `tps40100rger.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps40100) (41 pp, sha256 `022e07b23118d8ca`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps40100rger-datasheet.pdf)