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Contents

README

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TPS40057PWPR

Texas Instruments · DC-DC Converters · TSSOP-16-EP

TPS40057PWPR from Texas Instruments, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 KFF input Voltage feedforward and UVLO threshold programming input; connect resistor to VIN to set PWM ramp slope and programmable undervoltage lockout level.
2 RT input Switching frequency programming input; connect resistor to ground per formula fSW = 1/(17.82e-6*RT + 17) kHz.
3 BP5 power_out 5V reference output (4.7-5.2V nominal); bypass to ground with 0.1-µF ceramic capacitor, maximum 1 mA external DC load.
4 SYNC input External clock synchronization input; frequency must be 20-30% above programmed fSW, connect to SGND for free-run operation.
5 SGND power_in Signal ground reference for controller logic circuits; establish single-point connection to PGND for proper grounding separation.
6 SS/SD input Soft-start and shutdown control input; capacitor charged at 2.3 µA, output regulation begins at 0.85V and completes at 1.55V, shutdown below 125 mV.
7 VFB input Inverting input to error amplifier; voltage maintained at 0.7V internal reference for closed-loop output voltage regulation.
8 COMP output Error amplifier output applied to PWM comparator; internally clamped above ramp peak to improve large-signal transient response.
9 PGND power_in Power ground reference for driver circuits; requires low-impedance path to MOSFET source for proper circuit operation.
10 LDRV output Synchronous rectifier N-channel gate driver output (0-10V); rise/fall times 24-96 ns with 2.2 nF load, minimum controllable pulse width 100 ns.
11 BP10 power_out 10V reference output (9-10.3V nominal) for synchronous rectifier gate drive; bypass with 1-µF ceramic capacitor, maximum 1 mA external DC load.
12 SW input Switched node sensing input monitoring VIN-SW voltage across high-side MOSFET during conduction; used for pulse-by-pulse current limit comparison.
13 HDRV output Floating high-side N-channel gate driver output switching between BOOST (on) and SW (off); rise/fall times 36-96 ns with 2.2 nF load.
14 BOOST power_out Boosted gate drive supply output (BOOST = SW + 9V nominal ±1.5V); 0.1-µF ceramic bypass capacitor to SW required for charge storage.
15 VIN power_in Main supply voltage input (8-40V operating range); quiescent current 1.5-3 mA with output drivers not switching and VFB ≥ 0.75V.
16 ILIM input Overcurrent threshold programming input; internal current sink (8.5-11.5 µA) through external resistor to VIN sets pulse-by-pulse current limit.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16-EP
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TPS40057PWPR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: tps40057pwpr-etched.step / tps40057pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40057pwpr.step / tps40057pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 8efd3db408deb44b, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF