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TPS3899DL30DSER

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Texas Instruments , WSON-6(1.5x1.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS3899DL30DSER

Texas Instruments · IC · WSON-6(1.5x1.5)

TPS3899DL30DSER from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CTR passive Capacitor programmable reset delay: a ground-referenced capacitor (0 to 10 µF allowed) sets the delay for RESET to deassert after returning from the reset condition.
2 CTS passive Capacitor programmable sense delay: a ground-referenced capacitor (0 to 10 µF allowed) sets the delay for RESET to assert, and it also acts as a debouncer/manual reset input.
3 GND power_in Ground.
4 VDD power_in Supply voltage pin, 0.85 V to 6 V for DL outputs; place a 0.1 µF ceramic capacitor close to this pin.
5 SENSE input Monitored voltage input (connected directly for fixed variants or via resistor divider for the adjustable variant); RESET asserts after the CTS delay when it falls below VIT- and deasserts after the CTR delay once it rises above VIT- + VHYS, and a 10 nF to 100 nF capacitor close to the pin may be needed in noisy applications.
6 RESET output Open-drain active-low reset output (DL variant) that asserts low after the CTS delay when SENSE is below VIT- and stays low until SENSE rises above VIT- + VHYS and the CTR delay expires; requires an external pull-up resistor and can be pulled up to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6(1.5x1.5)
Category
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage (Open Drain Low) VDD 0.85 6 V 7
Negative-going input threshold range for all output configs VIT- 0.8 5.4 V 7
VIT- accuracy VIT- -2 0.5 2 % VIT- = 1.8 V to 5.4 V (Fixed threshold) 7
Hysteresis on VIT- VHYS 3 5 7 % VIT- = 0.9 V to 5.4 V 7
Current into Sense pin, fixed threshold version ISENSE 0.025 0.1 µA VDD = VSENSE = 6 V 7
Supply current into VDD pin when sense pin is separate IDD 0.125 1 µA VDD = VSENSE = 6 V, VIT- = 0.505 V and 0.8 V to 5.4 V 7
Power on reset voltage VPOR 700 mV VOL(max) = 300 mV, IRESET(Sink) = 15 µA 7
Low level output voltage (VDD = 0.85 V) VOL 300 mV VDD = 0.85 V, IRESET(Sink) = 15 µA 7
Low level output voltage (VDD = 3.3 V) VOL 300 mV VDD = 3.3 V, IRESET(Sink) = 2 mA 7
Open-drain output leakage current Ilkg(OD) 10 100 nA VDD = VPULLUP = 6 V, TA = -40℃ to 85℃ 7
Open-drain output leakage current Ilkg(OD) 10 350 nA VDD = VPULLUP = 6 V 7
Startup Delay tSTRT 300 µs CTR pin = Open or NC 8
Detect time delay tD-SENSE 30 50 µs CTS pin = Open or NC 8
Reset time delay tD 40 80 µs CTR pin = Open or NC 8
Glitch immunity tGI_VIT- 10 µs VIT- 5% VIT- overdrive 8
Detect time delay tD-SENSE 6.2 ms CTS pin = 10 nF 8
Detect time delay tD-SENSE 619 ms CTS pin = 1 µF 8
Reset time delay tD 6.2 ms CTR pin = 10 nF 8
Reset time delay tD 619 ms CTR pin = 1 µF 8
Voltage threshold to stop CTS capacitor charge and assert RESET VTH_CTS 0.73 V 0.73 * VDD 7
Voltage threshold to stop CTR capacitor charge and deassert RESET VTH_CTR 0.73 V 0.73 * VDD 7
CTS pin internal pull up resistance RCTS 500 kΩ 7
CTR pin internal pull up resistance RCTR 500 kΩ 7
Abs max voltage VDD, SENSE -0.3 6.5 V 5
Abs max voltage CTR, CTS -0.3 6.5 V VDD+0.3 V or 6.5 V, whichever is smaller 5
Abs max voltage RESET (open-drain) -0.3 6.5 V 5
Abs max current RESET pin -20 20 mA 5
Operating ambient temperature TA -40 125 °C 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V ANSI/ESDA/JEDEC JS-001 5
ESD CDM V(ESD) -750 750 V JESD22-C101 5
Recommended voltage VDD, SENSE 0 6 V 5
Recommended voltage CTR, CTS 0 6 V 0 to VDD 5
Recommended voltage RESET (TPS3899DL) 0 6 V 5
Recommended RESET pin current 0 5 mA printed 0 to ±5 mA 5
Operating free air temperature TA -40 125 °C 5
CTR pin capacitor range CCTR 0 10 µF 5
CTS pin capacitor range CCTS 0 10 µF 5
Junction-to-ambient thermal resistance RθJA 214.9 °C/W DSE, 6 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 153.7 °C/W DSE, 6 pins 6
Junction-to-board thermal resistance RθJB 112.3 °C/W DSE, 6 pins 6
Junction-to-top characterization parameter ψJT 25.5 °C/W DSE, 6 pins 6
Junction-to-board characterization parameter ψJB 111.8 °C/W DSE, 6 pins 6

CAD (KiCad official)

  • Symbol: TPS3899DL30DSER
  • Footprint: Package_SON:WSON-6_1.5x1.5mm_P0.5mm
  • 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
  • 3D model files: tps3899dl30dser-etched.step / tps3899dl30dser-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3899dl30dser.step / tps3899dl30dser.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 c0d1fba12d0813d6, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF