Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TPS3852G18QDRBRQ1

Texas Instruments · Supervisor And Reset ICs · SON-8-EP(3x3)

TPS3852G18QDRBRQ1 from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Supply voltage pin with a 1.6 V to 6.5 V recommended operating range, and a 0.1-μF bypass capacitor is recommended for noisy systems.
2 CWD passive Programmable watchdog timeout input: a capacitor of 0.1 nF to 1000 nF to ground sets the window watchdog upper boundary, while a 10-kΩ resistor to VDD or leaving the pin unconnected selects the preset timeouts.
3 MR input Manual reset input: a logical low issues a RESET, the pin is internally pulled up to VDD, and RESET stays low for the fixed reset delay tRST after MR goes high, with a 0 V to 6.5 V pin voltage range.
4 GND power_in Ground pin, which is also internally connected to the thermal pad.
5 SET1 input Logic input where grounding SET1 disables the watchdog timer, with a 0 V to 6.5 V pin voltage range.
6 WDI input Watchdog input where a falling edge must occur between the tWDL(max) and tWDU(min) window boundaries so WDO does not assert; the input is ignored while RESET or WDO are low or the watchdog is disabled, and it cannot be left unconnected when the watchdog is disabled.
7 WDO output Watchdog output that goes low for tRST on a watchdog timeout and only asserts while RESET is high, requiring a 1-kΩ to 100-kΩ pullup to the desired rail with output current limited to 10 mA.
8 RESET output Reset output that goes low when VDD falls below the undervoltage threshold VITN and goes high after the RESET timeout completes, requiring a 1-kΩ to 100-kΩ pullup with pin current limited to 10 mA.
9 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SON-8-EP(3x3)
Category Power Management (PMIC)
Pins 9

CAD (KiCad official)

  • Symbol: TPS3852G18QDRBRQ1
  • Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
  • 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps3852g18qdrbrq1-etched.step / tps3852g18qdrbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3852g18qdrbrq1.step / tps3852g18qdrbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 2e24daa8b2f6c684, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF