TPS3851G33SDRBR from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Supply voltage pin with a recommended operating range of 1.6 V to 6.5 V, and a 0.1 µF bypass capacitor is recommended for noisy systems.
2	CWD	input	Programmable watchdog timeout input, where a capacitor to ground sets the timeout and a 10 kΩ resistor to VDD or leaving the pin unconnected selects preset timeouts.
3	MR	input	Manual reset input, where a logical low issues a RESET, the pin is internally pulled up, and RESET stays low for tRST after MR is deasserted high.
4	GND	power_in	Ground pin.
5	SET1	input	Logic input where grounding the pin disables the watchdog timer, and SET1 together with CWD selects the watchdog timeouts.
6	WDI	input	Watchdog input where a falling edge must occur before tWD expires, and it must be driven to VDD or GND and cannot be left unconnected when the watchdog is disabled.
7	WDO	output	Watchdog output that must be connected through a 1 kΩ to 100 kΩ pullup to VPU, goes low for tRST on a watchdog timeout, and is high-impedance when RESET goes low.
8	RESET	output	Reset output that must be connected through a 1 kΩ to 100 kΩ pullup to VPU, goes low when VDD falls below VITN, and stays low until VDD is above VITN+VHYST and the RESET timeout completes.
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SON-8-EP(3x3)
Category	Power Management (PMIC)
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply pin voltage	VDD	1.6		6.5	V		4
SET1 pin voltage	VSET1	0		6.5	V		4
Watchdog timing capacitor	CCWD	0.1		1000	nF	Footnotes 1 and 2 apply	4
Pullup resistor to VDD	CWD	9	10	11	kΩ		4
Pullup resistor, RESET and WDO	RPU	1	10	100	kΩ		4
RESET pin current	IRESET			10	mA		4
Watchdog output current	IWDO			10	mA		4
Junction temperature	TJ	-40		125	°C		4
Supply voltage range	VDD	-0.3		7	V		4
Output voltage range RESET, WDO		-0.3		7	V		4
Voltage range SET1, WDI, MR		-0.3		7	V		4
Voltage range CWD		-0.3			V	Maximum VDD + 0.3 V or 7.0 V, whichever is smaller (footnote 3)	4
Output pin current RESET, WDO		-20		20	mA		4
Input current (all pins)		-20		20	mA		4
Operating junction temperature	TJ	-40		150	°C	Footnote 2 applies	4
Operating free-air temperature	TA	-40		150	°C	Footnote 2 applies	4
Storage temperature	Tstg	-65		150	°C		4
Supply current	IDD		10	19	µA		5
Supply voltage	VDD	1.6		6.5	V	Footnotes 1-3 apply	5
Undervoltage threshold accuracy, entering RESET	VITN	-0.8		0.8	%	VDD falling	5
Hysteresis voltage	VHYST	0.2	0.5	0.8	%	VDD rising	5
MR pin internal pullup current	IMR	500	620	700	nA	VMR = 0V	5
Power-on reset voltage	VPOR			0.8	V	IRESET = 15µA, VOL(MAX) = 0.25V	5
CWD pin charge current	ICWD	347	375	403	nA	CWD = 0.5V	5
CWD pin threshold voltage	VCWD	1.196	1.21	1.224	V		5
RESET, WDO output low	VOL			0.4	V	VDD = 5V, ISINK = 3mA	5
RESET, WDO output leakage current, open-drain	ID			1	µA	VDD = VITN + VHYST, VRESET = VWDO = 6.5V	5
Low-level input voltage (MR, SET1)	VIL			0.25	V		5
High-level input voltage (MR, SET1)	VIH	0.8			V		5
CWD evaluation period	tINIT			381	µs	Refer to Section 7.1.1.2	6
Minimum MR, SET1 pin pulse duration		1			µs		6
Reset timeout period	tRST	170	200	230	ms		6
Watchdog timeout, CWD = NC, SET1 = 1	tWD	1360	1600	1840	ms	CWD = NC, SET1 = 1	6
Watchdog timeout, CWD = 10kΩ to VDD, SET1 = 1	tWD	170	200	230	ms	CWD = 10kΩ to VDD, SET1 = 1	6
Junction-to-ambient thermal resistance	RθJA		50.7		°C/W	DRB (VSON) 8 pins	5
Junction-to-case (top) thermal resistance	RθJC(top)		51.6		°C/W	DRB (VSON) 8 pins	5
Junction-to-board thermal resistance	RθJB		25.8		°C/W	DRB (VSON) 8 pins	5
Junction-to-top characterization parameter	ψJT		1.3		°C/W	DRB (VSON) 8 pins	5
Junction-to-board characterization parameter	ψJB		25.8		°C/W	DRB (VSON) 8 pins	5
Junction-to-case (bottom) thermal resistance	RθJC(bot)		7.1		°C/W	DRB (VSON) 8 pins	5

CAD (KiCad official)

Symbol: TPS3851G33SDRBR
Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
3D model files: tps3851g33sdrbr-etched.step / tps3851g33sdrbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3851g33sdrbr.step / tps3851g33sdrbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (36 pp, sha256 293159a68e80dcf9, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPS3851G33SDRBR

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3D Model

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