component
TPS3842A010DRLR
Public Made by Adomby adom
Texas Instruments , SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS3842A010DRLR
Texas Instruments · IC · SOT-563
TPS3842A010DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply voltage pin, operating range 1.9V to 42V. |
| 2 | SENSE | input | Sense input that monitors the input voltage against the internal threshold, rated 0V to 42V and decoupled from VDD. |
| 3 | RESET | output | Open-drain active-low reset output for the A variant; connect to a pull-up voltage through a pull-up resistor, rated up to 42V. |
| 4 | CTS | input | Capacitor-programmable sense delay (de-glitch) pin that sets the delay when asserting a reset condition, 0V to 5V. |
| 5 | GND | power_in | Ground pin. |
| 6 | CTR | input | Reset time delay pin; connect an external capacitor for adjustable delay or leave floating for the shortest delay, 0V to 5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Negative-going threshold accuracy, adjustable (700mV) | VITN | -1.5 | 0.5 | 1.5 | % | Adjustable internal threshold, VITP = 700mV | 6 |
| Hysteresis Voltage, 10% Variant | VHYS | 9.5 | 10 | 10.5 | % | 10% Variant | 6 |
| Supply Voltage | VDD | 1.9 | 42 | V | 6 | ||
| Supply current | IDD | 0.85 | 1.9 | µA | VDD = 12V, RESET or RESET = Not asserted | 6 | |
| Low level output voltage | VOL | 300 | mV | 1.9V ≤ VDD < 42V, IRESET (Sink) = 0.5mA | 6 | ||
| Open drain output leakage current | ILKG | 300 | nA | VDD = VRESET = 12V | 6 | ||
| Input current, SENSE pin, adjustable | ISENSE | 25 | nA | VSENSE = VIT, Adjustable version | 6 | ||
| Power on reset voltage (Undervoltage variants) | VPOR | 1.3 | V | VOL(max) = 0.25V, IRESET (Sink) = 15µA | 6 | ||
| Voltage VDD, VSENSE, VRESET | VDD | -0.3 | 50 | V | VDD, VSENSE, VRESET | 5 | |
| Voltage VCTR, VCTS | VCTR, VCTS | -0.3 | 5.5 | V | 5 | ||
| Current IRESET | IRESET | -40 | 40 | mA | printed as ±40 | 5 | |
| Operating junction temperature | TJ | -55 | 150 | °C | 5 | ||
| Operating free-air temperature | TA | -55 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001, printed ±2000 | 5 | |
| ESD CDM | V(ESD) | -750 | 750 | V | Charged device model, JESD22-C101, printed ±750 | 5 | |
| Supply voltage VDD | VDD | 1.9 | 42 | V | 5 | ||
| Voltage VSENSE, VRESET | VSENSE | 0 | 42 | V | VSENSE, VRESET | 5 | |
| Voltage VCTS, VCTR | VCTS | 0 | 5 | V | 5 | ||
| Current IRESET | IRESET | 0 | 10 | mA | 5 | ||
| Junction temperature (free-air temperature) | TA | -40 | 125 | ℃ | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 153.4 | °C/W | DRL 6 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 86.3 | °C/W | DRL 6 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 42.8 | °C/W | DRL 6 pins | 5 | ||
| Junction-to-top characterization parameter | ΨJT | 2.9 | °C/W | DRL 6 pins | 5 | ||
| Junction-to-board characterization parameter | ΨJB | 41.2 | °C/W | DRL 6 pins | 5 |
CAD (KiCad official)
- Symbol:
TPS3842A010DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tps3842a010drlr-etched.step/tps3842a010drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3842a010drlr.step/tps3842a010drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
3a7d26e26ef063d7, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS3842A010DRLR
**Texas Instruments** · IC · SOT-563
TPS3842A010DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply voltage pin, operating range 1.9V to 42V. |
| 2 | SENSE | input | Sense input that monitors the input voltage against the internal threshold, rated 0V to 42V and decoupled from VDD. |
| 3 | RESET | output | Open-drain active-low reset output for the A variant; connect to a pull-up voltage through a pull-up resistor, rated up to 42V. |
| 4 | CTS | input | Capacitor-programmable sense delay (de-glitch) pin that sets the delay when asserting a reset condition, 0V to 5V. |
| 5 | GND | power_in | Ground pin. |
| 6 | CTR | input | Reset time delay pin; connect an external capacitor for adjustable delay or leave floating for the shortest delay, 0V to 5V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Negative-going threshold accuracy, adjustable (700mV) | VITN | -1.5 | 0.5 | 1.5 | % | Adjustable internal threshold, VITP = 700mV | 6 |
| Hysteresis Voltage, 10% Variant | VHYS | 9.5 | 10 | 10.5 | % | 10% Variant | 6 |
| Supply Voltage | VDD | 1.9 | | 42 | V | | 6 |
| Supply current | IDD | | 0.85 | 1.9 | µA | VDD = 12V, RESET or RESET = Not asserted | 6 |
| Low level output voltage | VOL | | | 300 | mV | 1.9V ≤ VDD < 42V, IRESET (Sink) = 0.5mA | 6 |
| Open drain output leakage current | ILKG | | | 300 | nA | VDD = VRESET = 12V | 6 |
| Input current, SENSE pin, adjustable | ISENSE | | | 25 | nA | VSENSE = VIT, Adjustable version | 6 |
| Power on reset voltage (Undervoltage variants) | VPOR | | | 1.3 | V | VOL(max) = 0.25V, IRESET (Sink) = 15µA | 6 |
| Voltage VDD, VSENSE, VRESET | VDD | -0.3 | | 50 | V | VDD, VSENSE, VRESET | 5 |
| Voltage VCTR, VCTS | VCTR, VCTS | -0.3 | | 5.5 | V | | 5 |
| Current IRESET | IRESET | -40 | | 40 | mA | printed as ±40 | 5 |
| Operating junction temperature | TJ | -55 | | 150 | °C | | 5 |
| Operating free-air temperature | TA | -55 | | 150 | °C | | 5 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 5 |
| ESD HBM | V(ESD) | -2000 | | 2000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001, printed ±2000 | 5 |
| ESD CDM | V(ESD) | -750 | | 750 | V | Charged device model, JESD22-C101, printed ±750 | 5 |
| Supply voltage VDD | VDD | 1.9 | | 42 | V | | 5 |
| Voltage VSENSE, VRESET | VSENSE | 0 | | 42 | V | VSENSE, VRESET | 5 |
| Voltage VCTS, VCTR | VCTS | 0 | | 5 | V | | 5 |
| Current IRESET | IRESET | 0 | | 10 | mA | | 5 |
| Junction temperature (free-air temperature) | TA | -40 | | 125 | ℃ | | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 153.4 | | °C/W | DRL 6 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 86.3 | | °C/W | DRL 6 pins | 5 |
| Junction-to-board thermal resistance | RθJB | | 42.8 | | °C/W | DRL 6 pins | 5 |
| Junction-to-top characterization parameter | ΨJT | | 2.9 | | °C/W | DRL 6 pins | 5 |
| Junction-to-board characterization parameter | ΨJB | | 41.2 | | °C/W | DRL 6 pins | 5 |
## CAD (KiCad official)
- Symbol: `TPS3842A010DRLR`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files: `tps3842a010drlr-etched.step` / `tps3842a010drlr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3842a010drlr.step` / `tps3842a010drlr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps3842.pdf) (26 pp, sha256 `3a7d26e26ef063d7`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps3842a010drlr-datasheet.pdf)