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TPS3840PL33DBVR
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Texas Instruments Supervisor And Reset ICs, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS3840PL33DBVR
Texas Instruments · Supervisor And Reset ICs · SOT-23-5
TPS3840PL33DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Active-low push-pull reset output that is asserted low when MR is pulled low or VDD falls below VIT-, with the absolute maximum RESET voltage limited to VDD + 0.3 V and RESET current limited to +/-5 mA recommended (+/-70 mA absolute maximum). |
| 2 | VDD | power_in | Input supply voltage that the supervisor monitors, with a recommended operating range of 1.5 V to 10 V and an absolute maximum of 12 V. |
| 3 | GND | power_in | Ground reference pin for the device. |
| 4 | MR / NC | input | Active-low manual reset input that asserts RESET when pulled to logic low (VMR_L); it may be left floating, must not exceed VDD, and releases after the reset time delay tD when floating or at VMR_H. |
| 5 | CT | passive | Capacitor time-delay pin where an external capacitor to ground sets the reset time delay, with the pin left floating for the smallest fixed delay and an absolute maximum of 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Negative-going input threshold accuracy | VIT- | -1.5 | 1 | 1.5 | % | -40°C to 125°C | 6 |
| Hysteresis on VIT- pin | VHYS | 175 | 200 | 225 | mV | VIT- = 3.1V to 4.9V | 6 |
| Supply current into VDD pin | IDD | 300 | 700 | nA | VDD = 1.5V < VDD < 10V, VDD > VIT+, TA = -40°C to 125°C | 6 | |
| Manual reset logic low input | VMR_L | 600 | mV | 6 | |||
| Manual reset logic high input | VMR_H | 0.7 | V | 0.7VDD | 6 | ||
| Manual reset internal pull-up resistance | RMR | 100 | kΩ | 6 | |||
| CT pin internal resistance | RCT | 350 | 500 | 650 | kΩ | 6 | |
| Low level output voltage (push-pull active-low) | VOL | 200 | mV | 1.5V < VDD < 5V, VDD < VIT-, IOUT(Sink) = 2mA | 6 | ||
| High level output voltage (push-pull active-low) | VOH | 0.8 | V | 1.5V < VDD < 5V, VDD > VIT+, IOUT(Source) = 2mA; 0.8VDD | 6 | ||
| High level output voltage (push-pull active-low, 5V to 10V) | VOH | 0.8 | V | 5V < VDD < 10V, VDD > VIT+, IOUT(Source) = 5mA; 0.8VDD | 6 | ||
| Startup delay | tSTRT | 100 | 220 | 350 | µs | CT pin open | 7 |
| Propagation detect delay for VDD falling below VIT- | tP_HL | 15 | 30 | µs | VDD = VIT+ to (VIT-) - 10% | 7 | |
| Reset time delay, CT pin open | tD | 50 | µs | CT pin = open | 7 | ||
| Reset time delay, CT pin = 10nF | tD | 6.2 | ms | CT pin = 10nF | 7 | ||
| Reset time delay, CT pin = 1µF | tD | 619 | ms | CT pin = 1 µF | 7 | ||
| Glitch immunity | tGI_VIT- | 10 | µs | VIT- 5% VIT- overdrive | 7 | ||
| MR pin pulse duration to initiate reset | tMR_PW | 300 | ns | 7 | |||
| Propagation delay from MR low to reset | tMR_RES | 700 | ns | VDD = 4.5V, MR < VMR_L | 7 | ||
| Input supply voltage | VDD | 1.5 | 10 | V | 5 | ||
| RESET pin and RESET pin voltage | VRESET | 0 | 10 | V | 5 | ||
| RESET pin and RESET pin current | IRESET | 0 | 5 | mA | ±5 mA magnitude | 5 | |
| Junction temperature (free air temperature) | TJ | -40 | 125 | °C | 5 | ||
| Manual reset pin voltage | VMR | 0 | V | maximum VDD | 5 | ||
| Supply voltage VDD | VDD | -0.3 | 12 | V | 5 | ||
| RESET (TPS3840PL) voltage | VRESET | -0.3 | V | VDD + 0.3 | 5 | ||
| CT pin voltage | VCT | -0.3 | 5.5 | V | 5 | ||
| MR pin voltage | VMR | -0.3 | 12 | V | 5 | ||
| Current RESET pin and RESET pin | IRESET | -70 | 70 | mA | 5 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 187.5 | °C/W | DBV (SOT23-5) | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 109.2 | °C/W | DBV (SOT23-5) | 5 | ||
| Junction-to-board thermal resistance | RθJB | 92.8 | °C/W | DBV (SOT23-5) | 5 | ||
| Junction-to-top characterization parameter | ψJT | 35.4 | °C/W | DBV (SOT23-5) | 5 | ||
| Junction-to-board characterization parameter | ψJB | 92.5 | °C/W | DBV (SOT23-5) | 5 |
CAD (KiCad official)
- Symbol:
TPS3840PL33DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps3840pl33dbvr-etched.step/tps3840pl33dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3840pl33dbvr.step/tps3840pl33dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
bc66e11c84e5f3be, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).