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TPS3840DL41DBVRQ1

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Texas Instruments Supervisor And Reset ICs, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps3840dl41dbvrq1
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docs tps3840dl41dbvrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tps3840dl41dbvrq1: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json tps3840dl41dbvrq1: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md tps3840dl41dbvrq1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago
tps3840dl41dbvrq1-etched.fit.json tps3840dl41dbvrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps3840dl41dbvrq1-etched.glb tps3840dl41dbvrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps3840dl41dbvrq1-etched.step tps3840dl41dbvrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps3840dl41dbvrq1.glb Publish 0.1.0 · Ray 1mo ago
tps3840dl41dbvrq1.kicad_mod Publish 0.1.0 · Ray 1mo ago
tps3840dl41dbvrq1.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps3840dl41dbvrq1.lbr Publish 0.1.0 · Ray 1mo ago
tps3840dl41dbvrq1.step Publish 0.1.0 · Ray 1mo ago

TPS3840DL41DBVRQ1

Texas Instruments · Supervisor And Reset ICs · SOT-23-5

TPS3840DL41DBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET output Active-low, open-drain reset output. Asserted low when VDD falls below the negative voltage threshold (VIT- = 4.1 V typ.) or when MR is pulled to a logic low. Deasserts (high-Z) after the programmed delay time (tD) once VDD rises above VIT+ (VIT- + 200 mV) and MR is released. Requires an external pull-up resistor.
2 VDD power_in Input supply voltage and monitored rail. Operating range 1.5 V to 10 V; monitored against VIT- = 4.1 V typical with 200 mV hysteresis.
3 GND power_in Device ground reference.
4 MR input Manual Reset input, active low. Pull below VMR_L to force RESET asserted; float or pull above VMR_H for normal operation. Internal glitch immunity. May be left floating (NC) when not used.
5 CT passive Capacitor Time Delay pin. Connect an external capacitor between CT and GND to program the reset delay time tD from ~50 µs (no cap) up to ~6.2 s with a 10 µF capacitor. Leave floating for fastest reset.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TPS3840DL41DBVRQ1

CAD (KiCad official)

  • Symbol: TPS3840DL41DBVRQ1
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps3840dl41dbvrq1-etched.step / tps3840dl41dbvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3840dl41dbvrq1.step / tps3840dl41dbvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 d1c08cabc9934f88, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF