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TPS3840DL40DBVRQ1
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS3840DL40DBVRQ1
Texas Instruments · Supervisor And Reset ICs · SOT-23-5
TPS3840DL40DBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Active-low open-drain reset output (TPS3840DL): driven low when MR is pulled low or VDD falls below the negative threshold VIT-, and held low for the delay time tD after MR is floating or above VMR_L and VDD rises above VIT+; the absolute maximum rating for the DL RESET pin is -0.3 V to 12 V, with a recommended RESET pin current of 0 to ±5 mA. |
| 2 | VDD | power_in | Input supply voltage that the device monitors; recommended operating range is 1.5 V to 10 V, with an absolute maximum of -0.3 V to 12 V. |
| 3 | GND | power_in | Ground reference pin for the device. |
| 4 | MR / NC | input | Manual reset input: pull to a logic low (VMR_L) to assert RESET; leave floating or drive at VMR_H to allow RESET to release after tD, with VMR not to exceed VDD (recommended range 0 to VDD, absolute maximum 12 V), and it may be left floating when not in use. |
| 5 | CT | passive | Capacitor time-delay pin: connect an external capacitor to CT and GND to set the reset delay from 50 µs (no capacitor) to 6.2 s (10 µF); leave floating for the smallest fixed delay, with an absolute maximum of -0.3 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
CAD (KiCad official)
- Symbol:
TPS3840DL40DBVRQ1 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps3840dl40dbvrq1-etched.step/tps3840dl40dbvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3840dl40dbvrq1.step/tps3840dl40dbvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
cf309c7c640e17d6, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS3840DL40DBVRQ1
**Texas Instruments** · Supervisor And Reset ICs · SOT-23-5
TPS3840DL40DBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Active-low open-drain reset output (TPS3840DL): driven low when MR is pulled low or VDD falls below the negative threshold VIT-, and held low for the delay time tD after MR is floating or above VMR_L and VDD rises above VIT+; the absolute maximum rating for the DL RESET pin is -0.3 V to 12 V, with a recommended RESET pin current of 0 to ±5 mA. |
| 2 | VDD | power_in | Input supply voltage that the device monitors; recommended operating range is 1.5 V to 10 V, with an absolute maximum of -0.3 V to 12 V. |
| 3 | GND | power_in | Ground reference pin for the device. |
| 4 | MR / NC | input | Manual reset input: pull to a logic low (VMR_L) to assert RESET; leave floating or drive at VMR_H to allow RESET to release after tD, with VMR not to exceed VDD (recommended range 0 to VDD, absolute maximum 12 V), and it may be left floating when not in use. |
| 5 | CT | passive | Capacitor time-delay pin: connect an external capacitor to CT and GND to set the reset delay from 50 µs (no capacitor) to 6.2 s (10 µF); leave floating for the smallest fixed delay, with an absolute maximum of -0.3 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## CAD (KiCad official)
- Symbol: `TPS3840DL40DBVRQ1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps3840dl40dbvrq1-etched.step` / `tps3840dl40dbvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3840dl40dbvrq1.step` / `tps3840dl40dbvrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600493540778786816) (38 pp, sha256 `cf309c7c640e17d6`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps3840dl40dbvrq1-datasheet.pdf)