# TPS3840DL30DBVRQ1

**Texas Instruments** · Supervisor And Reset ICs · SOT-23-5

TPS3840DL30DBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Active-low open-drain reset output: it is driven low when MR is driven low or VDD falls below the negative threshold VIT-, and stays asserted for the delay time tD after MR is floating or above VMR_L and VDD rises above VIT+. |
| 2 | VDD | power_in | Input supply voltage that the device monitors; the recommended operating range is 1.5 V to 10 V. |
| 3 | GND | power_in | Ground reference pin. |
| 4 | MR | input | Manual reset input: pull to a logic low (VMR_L) to assert reset; it may be left floating when not in use, and VMR should not be higher than VDD. |
| 5 | CT | passive | Capacitor time-delay pin: a capacitor connected to GND programs tD from 50 µs (no capacitor) to 6.2 s (10 µF); leave it floating for the smallest fixed delay. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage VDD (absolute maximum) | VDD | -0.3 |  | 12 | V |  | 5 |
| RESET pin voltage TPS3840DL (absolute maximum) | RESET | -0.3 |  | 12 | V | TPS3840DL | 5 |
| Manual reset MR voltage (absolute maximum) | MR | -0.3 |  | 12 | V |  | 5 |
| CT pin voltage (absolute maximum) | CT | -0.3 |  | 5.5 | V |  | 5 |
| RESET pin and RESET pin current (absolute maximum) |  | -70 |  | 70 | mA |  | 5 |
| Operating junction temperature TJ (absolute maximum) | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature (absolute maximum) | Tstg | -65 |  | 150 | °C |  | 5 |
| Input supply voltage | VDD | 1.5 |  | 10 | V |  | 5 |
| RESET pin and RESET pin voltage | VRESET | 0 |  | 10 | V |  | 5 |
| RESET pin and RESET pin current | IRESET | -5 |  | 5 | mA |  | 5 |
| Junction temperature (free air temperature) | TJ | -40 |  | 125 | °C |  | 5 |
| Manual reset pin voltage | VMR | 0 |  |  | V | upper limit is VDD | 5 |
| Negative-going input threshold accuracy | VIT- | -1.5 | 1 | 1.5 | % | -40°C to 125°C | 6 |
| Hysteresis on VIT- pin | VHYS | 75 | 100 | 125 | mV | VIT- = 1.6 V to 3.0 V | 6 |
| Supply current into VDD pin | IDD |  | 300 | 700 | nA | 1.5 V < VDD < 10 V; VDD > VIT+; TA = -40°C to 125°C | 6 |
| Manual reset logic low input | VMR_L |  |  | 600 | mV |  | 6 |
| CT pin internal resistance | RCT | 350 | 500 | 650 | kΩ |  | 6 |
| Power on reset voltage (open-drain) | VPOR |  |  | 950 | mV | VOL(max) = 0.2 V; IOUT(Sink) = 5.6 uA | 6 |
| Low level output voltage (open-drain) | VOL |  |  | 200 | mV | 1.5 V < VDD < 5 V; VDD < VIT-; IOUT(Sink) = 2 mA | 6 |
| Open-drain output leakage current | Ilkg(OD) |  |  | 90 | nA | RESET pin in High Impedance, VDD = VRESET = 5.5 V; VIT+ < VDD | 6 |
| Startup delay | tSTRT | 100 | 220 | 350 | µs | CT pin open | 7 |
| Propagation detect delay for VDD falling below VIT- | tP_HL |  | 15 | 30 | µs | VDD = VIT+ to (VIT-) - 10% | 7 |
| Manual reset internal pull-up resistance | RMR |  | 100 |  | kΩ |  | 6 |
| Reset time delay | tD |  | 50 |  | µs | CT pin = open | 7 |
| Reset time delay | tD |  | 6.2 |  | ms | CT pin = 10 nF | 7 |
| Reset time delay | tD |  | 619 |  | ms | CT pin = 1 µF | 7 |
| Glitch immunity on VIT- | tGI_VIT- |  | 10 |  | µs | VIT- 5% VIT- overdrive | 7 |
| MR pin pulse duration to initiate reset | tMR_PW |  | 300 |  | ns |  | 7 |
| Propagation delay from MR low to reset | tMR_RES |  | 700 |  | ns | VDD = 4.5 V, MR < VMR_L | 7 |
| Junction-to-ambient thermal resistance | RθJA |  | 187.5 |  | °C/W | DBV (SOT23-5) | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 109.2 |  | °C/W | DBV (SOT23-5) | 5 |
| Junction-to-board thermal resistance | RθJB |  | 92.8 |  | °C/W | DBV (SOT23-5) | 5 |

## CAD (KiCad official)

- Symbol: `TPS3840DL30DBVRQ1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps3840dl30dbvrq1-etched.step` / `tps3840dl30dbvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3840dl30dbvrq1.step` / `tps3840dl30dbvrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/ds/symlink/tps3840-q1.pdf) (39 pp, sha256 `bcbd6b6ff60acd14`, retrieved 2026-11-05, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps3840dl30dbvrq1-datasheet.pdf)